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PHY (TC-PMD) USER NETWORK INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS
Integrated Device Technology, Inc.
ADVANCED INFORMATION IDT77155
KEY FEATURES
* One chip ATM User Network Interface for 155.52 Mbps/ 51.84Mbps operating speed. * Full implementation of the SONET/SDH criteria according to Bellcore GR-253-CORE and ITU-T G.709, G.783. * Full implementation of the ATM physical layer according to CCITT I.432 and ATM Forum User Network Interface Specification. * Full-duplex 155.52 Mbps STS-3c/STM-1 or 51.84 Mbps STS-1 data with built-in clock/data recovery and clock synthesis. * Supports 4-cell PHY FIFO buffers for both transmit and receive directions with parity. * Provides GFC bits insertion and extraction. * UTOPIA Level 1 and Level 2 Interface. SYSTEM-LEVEL FUNCTIONAL BLOCK DIAGRAM
* Supports up to 4 PHYs for Multi-PHY connections with 2bit address and 8-bit data using UTOPIA 2 protocol. * Provides an 8-bit microprocessor bus interface for configuration, control and monitoring. * Low power CMOS * 128 pin PQFP Package (14 mm x 20 mm).
DESCRIPTION
The IDT77155 is a member of IDT's SWITCHStARTM family of products for Asynchronous Transfer Mode (ATM) networks. The IDT77155 is a integrated circuit that provides the SONET/SDH processing and ATM mapping functions of a 155 Mbps/51 Mbps ATM User Network Interface. Provides full compliance with SONET/SDH requirements and ATM Forum
RATE1 RATE0
XOFF TGFC TCP
TFPO
ATP2 TBYP
TCLK
TRCLKTFCLK timsnarT MTA lleC OFIF TXPRTY TDAT[7:0] TSOC TCA TxADDR[1:0] MPHYEN RxADDR[1:0] TSEN RFCLK RXPRTY RDAT[7:0] RSOC RCA Transmit UTOPIA Cell FIFO Transmit SONET Framer Parallel to Serial Clk Gen. TRCLK+ TXCTXC+ redocnE
RBYP
Encoder
TXD+ TXDRXDORXD-
Receive UTOPIA Cell FIFO
Decoder Receive SONET Framer Serial to Parallel Clk Rec. Micoprocessor Interface .ceR klC
RXD+ RXDO+ RRCLKRRCLK+ ALOSALOS+
RCP RGFC
RALM
ALE A[7:0] D[7:0]
RCLK
LFO LF- LF+ APT1
RFP
3497 drw 01
NICStAR is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
(c)1996 Integrated Device Technology, Inc.
NOVEMBER 1996
DSC-2066/5
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IDT77155 155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
ADVANCED INFORMATION Commercial Temperature Range
User Network Interface specifications. The IDT77155 provides both Transmission Convergence (TC) and Physical Media Dependent (PMD) sublayer functions of a 155.52 Mbps/51.84 Mbps ATM PHY suitable for ATM networks. The SONET/SDH interface provides the SONET/SDH overheads demultiplex and multiplex processing functions. The UTOPIA interface provides standardized
control and communications to other components, such as Segmentation and Reassembly (SAR) controllers and ATM switches. The IDT77155 is fabricated using state-of-the-art CMOS technology, providing the highest levels of integration, performance and reliability, with the low-power consumption characteristics of CMOS.
PACKAGE PINOUT
GND ALE A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] D[7] D[6] D[5] D[4] Vcc GND D[3] D[2] D[1] D[0]
Vcc GND
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
GND TBYP ATP2 AVcc AGND AVcc AGND AVcc TRCLKTRCLK+ AGND TXVcc TXC+ TXCTXD+ TXDTXGND Vcc GND Vcc GND RXDO+ RXDOAVcc RXDRXD+ ALOSALOS+ AGND AVcc AGND AVcc RRCLKRRCLK+ AGND AVcc AGND GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103
GND
IDT77155 TOP VIEW PX-128
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
GND
VCLK RATE[0] RATE[1] TSOC TXPRTY TDAT[7] TDAT[6] TDAT[5] TDAT[4] TDAT[3] TDAT[2] TDAT[1] TDAT[0] TCA TFCLK RSOC RXPRTY Vcc GND RDAT[7] RDAT[6] RDAT[5] RDAT[4] RDAT[3] RDAT[2] Vcc GND RDAT[1] RDAT[0] RCA RFCLK TSEN GND
3497 drw 02
GND ATP1 RBYP LF+ LFLFO RXADDR[1] RXADDR[0] TXADDR[1] TXADDR[0] MPHYEN XOFF TCP TGFC TFPO TCLK Vcc GND RCLK RFP RGFC RCP Vcc GND RALM GND
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IIDT77155 155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
ADVANCED INFORMATION Commercial Temperature Range
PACKAGE DIMENSIONS
128 Draft Angle = 11-13 1 A2 A1 e
0.20 Rad Typ.
128-Pin PQFP
E1 9'-5" 8'-7" E
0.20 Rad Typ.
4 4 A 2'-0"
L D1 5'-10" D 6'-8"
b
3445 drw 03
DIMENSIONS 128-PIN PQFP DImension Tolerance Letter (mm) A Max. +.10 A1 A2 +.17 D +.25 +.10 D1 E +.25 E1 +.10 L +15 e Basic b .05 Dimension (mm) 3.30 0.35 2.70 17.20 14.00 23.20 20.00 0.75 0.50 0.22
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IDT77155 155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
ADVANCED INFORMATION Commercial Temperature Range
PIN DESCRIPTIONS
Symbol A0-A7 Name Address I/O I Description Address bus to select specific registers in the register set. The address pin A7 has an integral pull-down resistor. Pin #: A0/119, A1/120, A2/121, A3/122, A4/123, A5/124, A6/125, A7/126 These pins should be physically isolated from the other ground pins. Pin #: 5, 7, 11, 29, 31, 35, 37 Latches the address bus when low, and is transparent when high. It allows interfacing to a multiplexed address/data bus. ALE has an integral pull-up resistor. Pin #: 127 Differential inputs indicate a loss of receive signal power. When ALOS+/- is asserted, data on the RXD+/- inputs is squelched and the receive data/clock recovery PLL switches to the reference clock. ALOS+/- has an effect only when RBYP is disabled. These inputs must be dc-coupled. Pin #: ALOS+ 28, ALOS- 27 Test pin for the transmit clock synthesis logic. When asserted, the TNB output of the clock synthesis block is reflected on the LFO pin. ATP1 has an integral pull-down resistor. Pin #: 40 Test pin for the receive clock/data recovery logic. When asserted, the CNB output of the clock recovery block is reflected on the LF-pin. ATP2 has an integral pull-down resistor. Pin #: 3 These power pins should be physically isolated from the other power pins and connected to a well coupled 5v dc source. Pin #: 4, 6, 8, 24, 30, 32, 36 Active low chip select to access registers. Pin #: 100 Bidirectional data bus for register access during register reads and writes. Pin #: D0/109, D1/110, D2/111, D3/112, D4/115, D5/116, D6/117, D7/118 Core, Ring and Thermal Grounds. Pin #: 1, 19, 21, 38, 39, 56, 62, 64, 65, 72, 80, 102, 103, 106, 113, 128 Open drain interrupt signal which goes low when an interrupt source is active and unmasked open from within the chip. This signal is cleared by appropriate reads to the interrupt registers. INT is an open-drain output. Pin #: 108 Special pin to output CAP voltage of the receive data/clock recovery logic when ATP2 is enabled. Reference clock signal of the receive data/clock recovery logic. Pin #: LF+/42, LF-/43 Special pin to output CAP voltage of the transmit clock synthesis logic when ATP1 is enabled. Pin #: 44 When asserted, the multiphy enable signal converts the UTOPIA interface to be fully compliant with the UTOPIA level-2 specification. In this mode, the TXADDR[1:0] and RXADDR[1:0] bits determine the address of the device to be addressed. The default operation of the chip is in single-phy UTOPIA level-1 mode. MPHYEN pin has an integral pulldown resistor. Pin #: 49 Output is asserted if line alarm indication signal (LAIS), path alarm indication signal (PAIS), loss of signal (LOS), loss of frame (LOF), or loss of cell delineation (LOC) is detected in the receive logic. RALM is updated on the rising edge of RCLK. Pin #: 63 RATE inputs select the frame format and line rates for both the transmit and receive functions RATE(1:0) 11 155.52 Mb/s, STS-3c / STM-1 10 51.84 Mb/s, STS-1 0X Reserved The RATE inputs have integral pull-up resistors, so the default is STS-3c Pin #: RATE0/98, RATE1/97
AGND ALE
Analog Ground Address Latch Enable Analog Loss of Signal
G I
ALOS+ ALOS-
I
ATP1
Test pin
I
ATP2
Test pin
I
AVcc
Analog Power
P
CS
Chip Select Data Ground Interrupt
I I/O G O
D1-D7 GND
INT
LF+ LFLFO MPHYEN
Loop Filter
O
Special Multi-phy Enable
O I
RALM
Receive Alarm
O
RATE0 RATE1
Line Rate
I
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IIDT77155 155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
ADVANCED INFORMATION Commercial Temperature Range
PIN DESCRIPTIONS (CONTINUED)
Symbol RBYP Name Receive Bypass I/O I Description Active high RBYP input disables clock recovery. If enabled, the receive different serial data RXD+/- is sampled on the rising edged of the receive differential reference clock RRCLK+/-. If RBYP is disabled, the receive clocks are recovered from RXD+/- bit stream. RBYP has an integral pull down resistor. Pin #: 41 This signal is asserted to indicate either 0 or a maximum of 4 morebytes are present in the tristate receive FIFO. The indication of the receive FIFO level is programmable, as is the polarity of this signal. Signal is updated on the rising edge of RFCLK. The RCA signal is tristated in UTOPIA level-2 mode (MPHYEN asserted) and driven as per the multi-phy protocol. Pin #: 69 Provides a timing reference, and is a divide-by-8 version of tri-covered clock when RBYP is disabled or RRCLK+/- when RBYP is enabled. Pin #: 57 Receive GFC pulse indicates the start of the four generic flow control bits (GFC) in the RGFC Pulse output. RCP is coincident with the most significant GFC bits. RCP is updated on the rising edge of RCLK. Pin #: 60 Active low read signal to read contents of addressed register. The data bus is driven by the contents of the addresses register when the read signal is asserted along with the chip select (CS) signal. Pin #: 105 The receive cell data to the ATM layer from the receive FIFO. This is updated on the rising edge of RFCLK. RDAT[7:0] is tristated if TSEN is asserted or if MPHYEN is asserted. In UTOPIA single-phy mode, it is driven if RRDENB is asserted (TSEN also asserted) or always driven if TSEN is low. In UTOPIA multi-phy mode, RDAT[7:0] is driven following the level-2 protocol. Pin #: RDAT0/70, RDAT1/71, RDAT2/74, RDAT3/75, RDAT4/76, RDAT5/77, RDAT6/78, RDAT7/79 The receive ATM clock from the ATM layer <= 40 MHz. The start of cell indication, the transmit data, and the transmit data parity signals are updated on the rising edge of this clock. RRDENB is sampled on the rising edge of this clock. Pin #: 67 An 8 KHz signal synchronized to RCLK. It is pulse high for one clock every 2430 RCLK cycles for STS-3c or every 810 RCLK cycles for STS-1. It is updated on the rising edge of RCLK. Pin #: 58 Outputs the extracted generic flow control bits (GFC) in a serial stream. The four GFC bits are output for each receive cell, and the first of the four bits is coincident with the RCP output, RGFC is low until cell delineation is achieved. RGFC is updated on the rising edge of RCLK. Pin #: 59 Inputs contain a jitter-free 19.44 MHz or a 6.48 MHz reference clock when clock recovery is enabled (RBYP = 0). When RBYP is enabled, RRCLK+/- is nominally a 155.52 MHz or 51.84 MHz 50% duty cycle clock and provides the timing for the internal receive functions. RXD+/- is sampled on the rising edge of RRCLK+/Pin #: RRCLK+/34/ RRCLK-/33 Active low signal from ATM signifying that data will be sampled on RDAT[7:0] in the following clock cycle. When sampled high, RSOC and RDAT[7:0] are tristated, if TSEN is enabled. RRDENB must operate with RFCLK at high rate to prevent receive FIFO overflow and loss of receive data. Pin #: 68
RCA/
RXEMPTY
Receive Cell Available
O
RCLK
Receive Clock
O
RCP
Receive Cell
O
RD
Read
I
RDAT0RDAT7
Receive Data
O
RFCLK
Receive FIFO Clock
I
RFP
Receive Frame Pulse
O
RGFC
Receive Generic O Flow Control
RRCLK+ RRCLK-
Receive Differential I Reference Clock
RRDENB
Receive Read Enable
I
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IDT77155 155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
ADVANCED INFORMATION Commercial Temperature Range
PIN DESCRIPTIONS (CONTINUED)
Symbol RSOC Name Receive Start of Cell I/O O Description Indication to the ATM layer. This is asserted during the first byte of each tristate cell and is updated on the rising edge of RFCLK. RSOC is tristated if TSEN is asserted or if MPHYEN is asserted. In UTOPIA single-phy mode, it is driven if RRDENB is asserted (TSEN also asserted) or always driven if TSEN is low. In UTOPIA multi-phy mode, RSOC is driven following the level-2 protocol. Pin #: 83 Active low asynchronous reset from the system. RST has integral pull-up resistor. RST need not be asserted to reset the chip. Pin #: 101 Receive address indicates the ID of the device which should respond to the receive bus signals in UTOPIA level-2 multi-phy mode (when MPHYEN is asserted). It indicates the device which should drive the receive cell to ATM device. The device ID may be programmed in a receive ID register. The device ID register contain a default address of 0. RXADDR[1:0] is sampled on the rising edge of RFCLK. RXADDR[1:0] inputs have integral pull-up resistors. RXADDR[1:0] inputs are ignored when MPHYEN is not asserted. Pin #: RXADDR0/46, RXADDR1/45 NRZ encoded receive differential data inputs which contain STS-3c or STS-1 data, and sampled on the rising edge of RRCLK+/- if RBYP asserted, else the receive clock are recovered from the data stream. Pin #: RXD+/26, RXD-/25 Sliced versions of the RXD+/- inputs, to allow decision feedback equalization (DFE) to correct baseline wander. These outputs could be programmed to be pure PECL. Defaults is a rail-to-rail swing. Pin #: RXDO+/22, RXDO-/25 Indicates the parity of the RDAT[7:0] bus. Odd or even parity may be selected. Tristate RXPRTY is enabled on the rising edge of RFCLK, RXPRTY is tristate if TSEN is asserted or if MPHYEN is asserted. In UTOPIA single-phy mode, it is driven if RRDENB is asserted (TSEN also asserted) or always driven if TSEN is low. In UTOPIA multi-phy mode, RXPRTY is driven following the level-2 protocol. Pin #: 82 Active high transmit bypass input disables clock generator. If enabled, the clock inputs TRCLK+/- become the transmit line lock at 155.52 MHz or 51.84 MHz. If disabled, the transmit clock is synthesized from a 19.44 MHz or 6.48 MHz reference clock on TRCLK+/-. TBYP has an integral pull down resistor. Pin #: 2 Signal indicates the availability of a complete cell space in the transmit FIFO. This signal when asserted indicates a maximum of 4 more transmit data writes will be accepted or that the transmit FIFO is full and no more writes will be accepted. The indication of the transmit FIFO level is programmable, as is the polarity of this signal. The FIFO depth at which the TCA signal indicates the unavailability of data space in the FIFO may be set to one, two, three, or four cells. TCA is updated on the rising edge of TFCLK. Pin #: 86 The transmit byte clock provides a timing reference, and is a divide-by-8 version of the synthesized clock when TBYP is disabled or TRCLK+/- when TBYP is enabled. Pin #: 54 Transmit GFC cell pulse indicates the expected place of the transmit GFC bits. TCP is updated on the rising edge of TCLK. Pin #: 51 The transmit cell data from the ATM layer sampled on the rising edge of TFCLK. It carries the 53 cell bytes. It is considered valid only when the TWRENB signal is asserted. Pin #: TDAT0/87, TDAT1/88, TDAT2/89, TDAT3/90. TDAT4/91, TDAT5/92, TDAT6/93. TDAT7/94 The transmit ATM clock from the ATM layer <= 40 MHz. The start of cell indication, the transmit data, the transmit data parity, and the enable signals are sampled on the rising edge of this clock. Pin #: 84
RST
Reset
I
RXADDR[0] RXADDR[1]
Receive Address
I
RXD+ RXD-
Receive Differential Data Inputs Receive Differential Data Outputs Receive Parity
I
RXDO+ RXDO-
O
RXPRTY
O
TBYP
Transmit Bypass
I
TCA/
TXFULL
Transmit Cell Available
O
TCLK
Transmit Clock
O
TCP
Transmit Cell Pulse Transmit Cell Data
O
TDAT[0]TDAT[7]
I
TFCLK
Transmit FIFO Clock
I
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IIDT77155 155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
ADVANCED INFORMATION Commercial Temperature Range
PIN DESCRIPTIONS (CONTINUED)
Symbol TFPO Name Transmit Framing Position Output I/O O Description Transmit frame pulse is an 8 KHz signal synchronized to TCLK. It is pulsed high for one clock every 2430 TCLK cycles for STS-3c or every 810 TCLK cycles for STS-1. It is updated on the rising edge of TCLK. Pin #: 53 Input provides the ability to insert GFC values downstream of the transmit FIFO. The four TCLK periods following TCP output pulse should contain the four GFC bits to be inserted. The GFC enable bits in a configuration register enable the insertion of each bit. By default, the GFC values contain the header information of the default idle/unassigned cell header register. The inserted GFC bits are input into the next immediate cell to be transmitted. TGFC bits are sampled on the rising edge of TCLK. Pin #: 52 Differential input contain a jitter-free 19.44 MHz or a 6.48 MHz reference clock when clock synthesis is enabled (TBYP = 0). When TBYP is enabled, TRCLK+/- is nominally a 155.52 MHz or 51.84 MHz 50% duty cycle clock and provides the timing for the internal transmit functions. It may be left unconnected if loop timing is enabled. Pin #: TRCLK+/10, TRCLK-/9 The tristate enable signal tristates RSOC, RDAT[7:0], and RXPRTY signals. When asserted, RSOC, RDAT[7:0], and RXPRTY are driven only when RRDENB is asserted. When TSEN is low, the signals RSOC, RDAT[7:0], and RXPRTY, are always asserted in single-phy UTOPIA level-1 mode. TSEN has an integral pull-down resistor. Pin #: 66 The transmit start of cell indication from ATM layer. This should be asserted during the first byte of each cell and is sampled on the rising edge of TFCLK. An interrupt is generated while TSOC is asserted at any byte other than the first byte of the transmit 53 byte cell. Pin #: 96 Active low transmit enable signal used to initiate writes to the transmit FIFO from the ATM device. When asserted low, the byte on TDAT[7:0] is written to the transmit FIFO. A complete 53 byte cell must be written to the FIFO before the cell is inserted into the SPE of the transmit frame. Idle/unassigned cells are inserted until a complete cell is available for transmission. Pin #: 85 Indicates the ID of the device which should respond to the transmit bus signals in transmit bus signals in UTOPIA level-2 multi-phy mode (when MPHYEN is asserted). It indicates the device which should accept the transmit cell from ATM device. The device ID may be programmed in a transmit ID register. The device ID register contain a default address of 0. TXADDR[1:0] is sampled on the rising edge of TFCLK. TXADDR[1:0] inputs have integral pull-up resistors. TXADDR[1:0] inputs are ignored when MPHYEN is not asserted. Pin #: TXADDR0/48, TXADDR1/47 Transmit differential line negative output clock is a buffered version of the input differential clock. These outputs could be programmed to be pure PECL. Default is a rail-to-rail swing, If these outputs are not programmed to be PECL, then the outputs are squelched in the STS-3c mode. Pin #: TSC+/13, TXC-/14 NRZ encoded transmit differential data outputs which contain STS-3c or STS-1 data, and updated on the falling edge of TXC+/-. These outputs could be programmed to be pure PECL. Default is a rail-to-rail swing. Pin #: TXD+/15, TXD-/16 Indicates the parity of the TDAT[7:0] bus. Odd or even parity may be selected. TXPRTY is sampled on the rising edge of TFCLK and considered valid only when TWRENB is asserted. TXPRTY has an integral pull-down resistor. A maskable parity error is generated if an error is detected, but the cells with parity errors are not filtered. Pin #: 95 Power pin for TXC+/- and TXD+/- outputs. Should be physically isolated from the other power analog pins and connected to a well coupled 5v dc source. Pin #: 12
TGFC
Transmit Generic Flow Control
I
TRCLK+ TRCLK-
Transmit Reference Clock
I
TSEN
Transmit Enable
I
TSOC
Transmit Start of Cell
I
TWRENB
Transmit Write Enable
I
TXADDR[0] TXADDR[1]
Transmit Address
I
TXC+ TXC-
Transmit Clock
O
TXD+ TXD-
Transmit Data
O
TXPRTY
Transmit Parity
I
TXVcc
Power
P
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IDT77155 155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
ADVANCED INFORMATION Commercial Temperature Range
PIN DESCRIPTIONS (CONTINUED)
Symbol TXGND Name Ground I/O G Description Ground pin for TXC+/- and TXD+/- outputs. Should be physically isolated from the other ground analog pins. Pin #: 17 Core and pad ring power connected to a decoupled 5V dc Pin #: 18, 20, 55, 61, 73, 81, 107, 114 VCLK is used as a test mode input to the chip. It should be asserted only when testing the chip on a tester. It shortens the count values for most receive error counters to enable the testing to be done in a reasonable amount of time. VCLK has an intergral pull-down registor. Pin #: 99 Active low write signal to update registers. The data bus contents are latched into the addressed register on the rising edge of the write signal when the chip select (CS) is asserted. Pin #: 104 Transmit off signal prevents the insertion of cells from the transmit FIFO into the transmit frames. If asserted, idle/unassigned cells only are transmitted irrespective of the state of the transmit FIFO. XOFF is an asynchronous signal and has an integral pull-down registor. Pin #: 50
Vcc VCLK
Power Vector Clock
P I
WR
Write
I
XOFF
Transmit Off
I
Notes 1. All inputs operate at TTL levels except the PECL inputs. 2. RDAT[7:0], RXPRTY, RCP, RGFC, RSOC, TCA, TCLK, RCLK, TCP outputs have an 8 ma drive capability, while all other digital outputs have 4 ms drive. 3. All analog power/ground pins should be isolated from the digital power/ground pins, preferably with separate power supplies. It is recommanded to have separate ground planes on the board also.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM TA TBIAS TSTG IOUT Rating Commercial Unit V C C C mA Terminal Voltage -0.5 to +7.0 with respect to DVGND Operating Temperature Temperature Under Bias Storage Temperature DC Output Current 0 to +70 -55 to +125 -55 to +125 50
CAPACITANCE (TA = +25C)
Symbol CIN
(1)
Parameter Input Capacitance Output Capacitance
Conditions VIN = 0V VOUT = 0V
Max. 10 10
Unit pF pF
COUT(1)
NOTE: 1. Characterized values, not currently tested.
3139 tbl 05
NOTE: 3139 tbl 02 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliabilty.
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IIDT77155 155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
ADVANCED INFORMATION Commercial Temperature Range
DC ELECTRICAL CHARACTERISTICS
Symbol VCC GND VILp VIHp VOLp VOHp VIL VIH VOL VOH AVCC AGND IDD1 Parameter Digital Supply Voltage Digital Ground Voltage PECL Input Low Voltage PECL Input High Voltage PECL Output Low Voltage PECL Outut High Voltage TTL Input Low Voltage TTL Input High Voltage TTL Output Low Voltage TTL Output High Voltage Analog Supply Voltage Analog Ground Voltage Power Supply Current Min. 4.5 0 Vcc-1.8V Vcc-1.0V Vcc-1.8V Vcc-1.0V -- 2.0 -- 2.4 4.5 0 -- Typ. 5.0 0 -- -- -- -- -- -- -- -- 5.0 0 -- Max. 5.5 0 Vcc-1.6V Vcc-0.8V Vcc-1.6V Vcc-0.8V 0.8 -- 0.4 -- 5.5 0 Unit V V V V V V V V V V V V
85 (155.52Mbps) mA 55 (51.84Mbps) 100 A
IDD2
Average Standby Current
--
--
TABLE 1. B2 BER DETECTION CONFIGURATION TABLE
Desired BER trigger 1e-3 1e-4 1e-5 1e-6 1e-7 1e-8 1e-9 Desired detectiion time 0.008s 0.013s 0.100s 1.000s 10.00s 83.00s 667.0s Denominator multiple 0 0 20 989 7849 41615 52313 Window Length 64 104 38 8 10 16 102 BIP Threshold 19 2 4 19 15 7 1 Calculated BER trigger 0.988e-3 1.040e-4 0.991e-5 0.998e-6 0.994e-7 0.875e-8 0.994e-9 Calculated detectiopn time 0.008s 0.013s 0.0998s 0.990s 9.810s 83.23s 666.99s
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IDT77155 155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
ADVANCED INFORMATION Commercial Temperature Range
FUNCTIONAL DESCRIPTION
CLOCK RECOVERY The clock recovery Block recovers the clock from the receiving serial data stream. This block can be selected to utilize reference clocks at 6.48 MHz or 19.44 MHz. This unit provides a status bit to indicate whether it is locked to data or the reference clock. The clock recovery unit also provides a loss of signal (LOS) input and a diagnostic loopback. The PLL originally locks to the reference clock. The PPL will lock to the data when the frequency of the recovered clock is within 244 ppm of the reference clock. Once in data lock, the PLL switches to the reference clock if there is no data transition for an 80 bit period or the recovered clock drifts for over 244 ppm of the reference clock. The transmit clock could be derived from the recovered clock (loop timing) by configuration. SERIAL TO PARALLEL This block performs the serial to parallel conversion of incoming bit serial data into byte serial data. RECEIVE SONET FRAMER The Receive SONET Framer performs frame synchronization, descrambling, pointer interpretation, SONET section, line, and path overhead processing, alarm and performance monitoring functions. The framer determines the out-of-frame/in-frame status for the STS-3c/STS-1 data by checking the framing pattern (A1, A2). Out-of-frame is declared when four consecutive frames with errored framing patterns are received. While out-offrame, the framer searches for the correct framing pattern, inframe is declared upon detecting two consecutive error-free framing patterns. The Loss Of Frame (LOF) status is determined by monitoring the out-of-frame/in-frame conditions. This block provides the 3 ms out-of-frame timer and in-frame timer. The in-frame timer accumulates when the out-of-frame is absent; it stops accumulating and is reset to zero when the out-of-frame is present. The out-of-frame timer accumulates when the out-offrame is present; it stops accumulating when the out-of-frame is terminated. For the intermittent out-of-frame conditions, it is only reset to zero when the out-of-frame is absent continuously for 3 ms (i.e., the in-frame timer reaches 3 ms). The LOF is declared when the accumulated out-of-frame timer reaches 3 ms. Once detected, the LOF defect is terminated when the in-frame timer reaches 3 ms. The Loss Of Signal (LOS) Block checks the incoming scrambled data availability. LOS is declared when 20 + 3 s of all-zero pattern is detected. Loss of signal is cleared when two consecutive valid framing patterns is detected, and during the intervening time (one frame), no all-zero pattern qualifying as LOS defect exits. The incoming data stream is descrambled. The scrambling polynomial is 1 + x6 + X7 and the sequence length is 127. The
framing bytes (A1, A2) and the identity bytes (C1) are not descrambled. The descrambling function can be disable by a register control bit. The B1 BER is monitored by the incoming section BIP-8 error detection code (B1). The BIP-8 code is calculated over all bits of the complete STS-3c or STS-1 frame before descrambling by bit interleaved parity calculation using even parity. And obtains errors by comparing the calculated BIP-8 code with the BIP-8 code extracted from the B1 byte of the next incoming frame. Up to 64,000 (8 x 8000) bit errors can be detected for one second. One 16-bit saturating counter is provided to accumulate these BIP errors. This counter is to be read via microprocessor interface at least once per second for performance monitoring. The B2 BER is monitored by the incoming Line BIP-8/24 error detection code (B2). The BIP-8/24 code is calculated over all bits of the line overhead and synchronous payload envelope after descrambling by bit interleaved parity calculation using even parity. And obtains errors by comparing the calculated BIP-8/24 code with the BIP-8/24 code extracted from the B2 byte of the next incoming frame. Up to 192,000 (24 x 8000) bit errors can be detected for one second. One 20-bit saturating counter is provided to accumulate these BIP errors. This counter is to be read via microprocessor interface at least once per second for the performance monitoring. The defect detection for B2 EBER is also provided. The Receive B2 BER Detection Algorithm provides a method for detection of a preset Bit Error Rate (BER) in the incoming SONET/SDH data stream. Upon detection of the preset level, the IDT77155 can optionally assert its interrupt pin and provide status information. The algorithm provides two identical, programmable BER detection blocks that will allow the user to detect BER by setting two independent BER thresholds. This can be used to provide the "warning" and "fail" thresholds needed to comply with the SONET/SDH specification for Automatic Protection Switching (APS). To detect the BER for "warning" and "fail" level. Three configuration registers are provided respectively. Denominator (DM) register: 16-bit register, Number of frames (frames = DM + 1) that are used to compute the BER. Window Length (WL) register: 8-bit register, Length of the sliding window in frames. BIP Threshold (BT) register: 8-bit register, Value for the BIP threshold. The Denominator, Window Length, and BIP Threshold registers are configured according to Table 1 for "warning" and "fail" BER detection respectively. The first two rows are "fail" levels, and the remaining are "warning" levels. The Line Alarm Indication Signal (AIS) is detected in the incoming data stream. Line AIS is declared when five consecutive frames "111" pattern in bits 6-8 of K2 byte are detected. Line AIS is removed when five consecutive frames
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of any pattern other than "111" in bits 6-8 of K2 byte are detected. For SDH applications, Line AIS is declared when three consecutive frames "111" pattern in bits 6-8 of K2 byte are detected. Line AIS is removed when three consecutive frames of any pattern other than "111" in bits 6-8 of K2 byte are detected. The selection of SONET or SDH detection criteria is set by control register. The Line Remote Defect Indication (RDI) is detected in the incoming data stream. Line RDI is declared when five consecutive frames of "110" pattern in bits 6-8 of K2 byte are detected. Line RDI is removed when five consecutive frames of any pattern other than "110" in bits 6-8 of K2 byte are detected. For SDH applications, Line RDI is declared when three consecutive frames of "110" pattern in bits 6-8 of K2 byte are detected. Line RDI is removed when three consecutive frames of any pattern other than "110" in bits 6-8 of K2 byte are detected. The selection of SONET or SDH detection criteria is set by control register. K1 and K2 bytes are extracted if new identical values are received for 3 consecutive frames for Automatic Switch Protection (APS) use. The Line Far End Block Error (LFEBE) can be monitored by extracting the 8-bit FEBE from the incoming third Z2 byte. the error count range is from 0 to 24 errors. Any other value is counted as zero error. Up to 192,000 (24x 8000) bit errors can be detected for one second, One 20-bit saturating counter is provided to accumulate these FEBE errors. This counter is to be read and reset via microprocessor interface. The Pointer Interpreter interprets the incoming pointer byte (H1, H2) to determine the location of the J1 byte (path overhead) in the incoming STS-3c or STS-1 data stream. The Pointer Interpreter detects loss of pointer (LOP) and path AIS in the incoming STS-3c or STS-1 data stream. LOP is declared when eight consecutive invalid pointers or eight consecutive NDF enabled indications are detected. LOP is removed when three consecutive same valid pointers with normal NDF are detected. Path AIS is declared when three consecutive "all-one" pattern in H1 and H2 byte are detected. Path AIS is removed when three consecutive same valid pointers with normal NDF are detected or when a valid pointer with NDF enabled is detected. The B3 BER is monitored by the incoming Path BIP-8 error detection code (B3). The BIP-8 code is calculated over all bits of the synchronous payload envelope after descrambling by bit interleaved parity calculation using even parity. And obtains errors by comparing the calculated BIP8 code with the BIP-8 code extracted from the B3 byte of the
next incoming frame. Up to 64,000 (8 x 8000) bit errors can be detected for one second. One 16-bit saturating counter is provided to accumulate these BIP errors. This counter is to be read via microprocessor interface at least once per second for performance monitoring. C2 Mismatch is detected in the incoming data stream. C2 Mismatch is declared when five consecutive frames of the value other than "13h" in C2 byte are detected. C2 Mismatch is removed when five consecutive frames of the value "13h" in C2 byte are detected. The Path Far End Block Error (PFEBE) can be monitored by extracting the 4-bit FEBE from the incoming path status byte (G1). the error count range is from "0000" to "1000" to represent zero to eight errors. Any other value is counted as zero error. Up to 64,000 (8 x 8000) bit errors can be detected for one second, One 16-bit saturating counter is provided to accumulate these FEBE errors. This counter is to be read and reset via microprocessor interface. Path Remote Defect Indication (RDI-P) is detected by checking the bit 5 of path status byte (G1) in the incoming data stream. Path RDI is declared when ten consecutive frames of value "1" in bit 5 of G1 byte are detected. Path RDI is removed when ten consecutive frames of value "0" in bit 5 of G1 byte are detected.
RECEIVE UTOPIA CELL FIFO The Receive UTOPIA Cell FIFO provides functions for ATM cell delineation, HEC error verification, cell filtering, and ATM cell payload descrambling. This block also provides a four cell deep receive FIFO. Cell Delineation is for validating the HEC of a cell header by checking with the CRC-8 calculation over first 4 bytes of ATM cell header; the coset value of "55h" can be optionally added to the HEC during validation. HEC validation uses the state machine in CCITT recommendation I.432 and is shown in Figure 1. The state machine shown in Figure 1 is initialized to the HUNT state in which every byte of ATM 53 byte is checked for a valid HEC. Once correct HEC has been found, cell delineation state machine enters the PRESYNC state that validates HEC on a cell by cell basis. If additional DELTA (value is suggested to be six) consecutive correct HECs are validated, the state machine enters the SYNC state. However, if any incorrect HEC is found in the PRESYNC state, the state machine reverts to HUNT state. Once in SYNC state, it stays in the SYNC state until ALPHA (value is suggested to be seven) consecutive incorrect HECs are detected. HUNT state is entered and the search for a correct HEC on a byte by byte basis resumes. Cell could be discarded with HEC errors by using HEC
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verification while in SYNC state. The HEC verification state machine is shown in Figure 2. The state machine is initialized to "correction mode". Cells with no HEC errors are passed to the receive FIFO. Any single bit error detected in the incoming cell headers are corrected and the cells are passed. It enters into "detection mode" if any single bit or multi-bit errors in the header are detected. In "detection mode", all cells with single or multi-bit errors are dropped. Only cells with no errors are passed. When a cell with no HEC error is detected in "detection mode", it enters back to "correction mode". However, if seven consecutive cells with errored HEC are received, HUNT state is entered from the "detection mode". The ATM Descrambler descrambles the incoming 48 byte cell payload only (header is not descrambled) by using polynomial x43 + 1. The descrambling function may be disabled. One 8-bit saturating HEC correctable error counter, one 8bit saturating HEC uncorrectable error counter, and a 19-bit saturating receive cell counter are provided for ATM Cell performance monitoring . The HEC correctable error counter accumulates HEC single bit errors in the header. The HEC uncorrectable error counter accumulates HEC multiple bit errors in the header. The receive cell counter accumulates the number of assigned cells. All counters are active only in the SYNC state. These three counter are to be read via microprocessor interface at least once per second for performance monitoring. The received GFC bits are output in a serial stream via the GFC Extraction output. GFC bits are extracted for every received cell with the RCP output to indicate the position of the most significant bit. The GFC output may be disabled via the control register or no cell delineation. The Receive FIFO has four ATM cells depth. It provides FIFO management and the separation of STS-3c or STS-1 timing from ATM layer timing. The FIFO management functions are to fill the receive four cells FIFO and indicate when cells are ready to be read from the receive FIFO and to detect FIFO overflow and underflow. When overflow, the receive FIFO discards the incoming ATM cells, a maskable interrupt and status register also active for overflow condition. When underflow, the read is ignored. When FIFO data is read out by RFCLK, the start of cell (RSOC) is active. The cell available status (RCA) is provided to indicate a cell is available in the receive FIFO. CLOCK SYNTHESIS The Clock Generator generates the 155.52 or 51.84 MHz transmit clock by locking to a 1/8-frequency reference clock i.e., synthesized from a 19.44 MHz or 6.48 MHz reference clock. PARALLEL TO SERIAL This block performs the parallel to serial conversion to
convert the outgoing byte serial data to bit serial data. TRANSMIT SONET FRAMER The Transmit SONET Framer provides framing pattern (A1, A2) insertion, scrambling, pointer generation, SONET section, line and path overhead insertion, and alarm signal insertion. The Framing pattern (A1, A2) and C1 are inserted into outgoing STS-3c or STS-1 data stream. The framing bit error may be insert for diagnostic. The STS Scrambler scrambles the outgoing data except framing bytes (A1, A2) and identity byte (C1) by the using polynomial 1 + x6 + x7. Scrambling may be disabled via control register. An "all-zero" pattern may be inserted via microprocessor interface after scrambling for diagnostic information. The outgoing section BIP-8 error detection code (B1) is calculated over all bits of the complete STS-3c or STS-1 frame after scrambling by bit interleaved parity calculation using even parity. The calculated BIP-8 code is then inserted into the B1 byte of the next outgoing frame before scrambling. Corrupted BIP-8 code may be inserted via control register for diagnostic information. The Line AIS may be set for outgoing data stream by inserting "all-one" pattern into line overhead and Synchronous Payload Envelope (SPE) of STS-3c or STS-1 frame by control register via microprocessor interface. The Line Remote Defect Indication (RDI) may be set for outgoing data stream by inserting "110" pattern in bits 6-8 of K2 byte to generate Line RDI. K1 and K2 byte may be inserted for outgoing data stream for automatic switch protection (APS) use. The outgoing line BIP-8 error detection code (B2) is calculated over all bits of the line overhead and Synchronous Payload Envelope (SPE) of STS-3c or STS-1 frame before scrambling by bit interleaved parity calculation using even parity. The calculated BIP-8 code is then inserted to the B2 byte of the next outgoing frame before scrambling. Corrupted BIP-8 code may be inserted via control register for diagnostic information. The Line FEBE can be inserted by accumulating detected B2 BIP-8 errors from receive direction into FEBE code of the third Z2 byte for transmit STS-3c frame. The Pointer Generator generates the pointer (H1, H2) for outgoing STS-3c or STS-1 data stream. The "ss" bits of pointer is programmable for the SDH requirement. The location of start of the Synchronous Payload Envelope (SPE) is according to the value of generated pointer.
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The outgoing path BIP-8 error detection code (B3) is calculated over all bits of Synchronous Payload Envelope (SPE) of STS-3c or STS-1 frame before scrambling by bit interleaved parity calculation using even parity. The calculated BIP-8 code is then inserted to the B3 byte of the next outgoing frame before scrambling. Corrupted BIP-8 code may be inserted via control register for diagnostic. The C2 byte is set as "13h" by default for ATM mapping. Value of C2 may be set by control register via microprocessor. The Path FEBE can be inserted by accumulating detected B3 BIP-8 errors from receive direction into FEBE code of the path status byte (G1) for transmit STS-3c or STS-1 frame. Path FEBE may be inserted via control register for diagnostic information. The Path Remote Defect Indication (RDI) may be set for outgoing data stream by inserting "1" into bit 5 of path status byte (G1). H4 can be inserted by the value, which indicates the offset between H4 byte position and the ATM cell boundary of the first cell at the same row. Synchronous Payload Envelope (SPE) can be mapped into outgoing STS-3c or STS-1 frame according to the generating pointer. TRANSMIT UTOPIA CELL FIFO The ATM Scrambler scrambles the out going 48 byte cell payload only (header is not scrambled) by using polynomial x43 + 1. The scrambling function may be disabled.
The Idle Cell Generator Block inserts idle/unassigned cells into the transmit cell stream if a complete ATM cell was not written into the transmit FIFO. The GFC, PTI and CLP may be set via control registers. The "all-zero" pattern is inserted into the VCI/VPI of header. HEC of the idle cell is calculated and inserted. The HEC Generator calculates the CRC-8 code over the first four byte of header and inserts the CRC-8 code into the fifth byte of header. The polynomial x8 + x2 + x + 1 for HEC generation is used. The coset polynomial x6 + x4 + x2 + 1 is added to the residue. A 19-bit saturating transmit cell counter is provided for ATM cell performacne monitoring. The four serial GFC bits are inserted according to the framing pulse of the transmit cell. The value of GFC bits may be set by the control registers. The Transmit FIFO has four ATM cells depth. It provides FIFO management and the separation of STS-3c or STS-1 timing from ATM layer timing. The FIFO management functions are to fill the transmit four cells FIFO and indicate when cells are ready to be written into the transmit FIFO and to detect FIFO overflow condition. When the transmit FIFO contains four cells and the upstream device still writes cell into FIFO, the overflow condition will be indicated. A maskable interrupt and status register also active for overflow condition. The write signal and all data writing into FIFO are ignored until there is a space in FIFO. MICROPROCESSOR INTERFACE The Microprocessor Interface provides interface logic circuit and the registers for the functions of configuration, monitoring, control and test.
Figure 1. Cell Delineation State Diagram
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Figure 2. HEC Verification State Diagram
TFCLK
TSOC
TCA
TCALEVEL0 = 1
TDAT[0:7]
X
H1
H2
P44
P45
P46
P47
P48
X
H1
TXPRTY
X
X
Figure 3. Transmit Waveform for UTOPIA Interface
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RFCLK
RSOC
Z
RCA
RCALEVEL0 = 0
RDAT[0:7]
H1
H2
P44
P45
P46
P47
P48
X
H1
RXPRTY
X
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Figure 4. Re8.03 14
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TCLK
TCP
TGFC
X
GFC[3]
GFC[2]
GFC[1]
GFC[0]
X
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Figure 5. Transmit GFC Serial Link Waveform
RCLK
RCP
RGFC
X
GFC[3]
GFC[2]
GFC[1]
GFC[0]
X
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Figure 6. Receive GFC Serial Link Waveform
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OPERATION MODES
MULTI-PHY OPERATION Multiple IDT77155s may be connected to common bus when a Multi-PHY system architecture is needed. Both Transmit and Receive UTOPIA busses, as well as the utility bus, can attach to common busses. Device selection is controlled via the UTOPIA "enable" control signals ( TWRENB, RRDENB) and Multi-PHY addressing signals (TXADDR[1:0], RXADDR[1:0]). In transmit, TWRENB tells the selected device (selected by TXADDR[1:0]) that the data and control signals it sees are to be used for ATM cell transmission. In receive, when RRDENB is not asserted (active low), RDAT[7:0], RXPRTY, RSOC, and RCA are all tristated, allowing them to share a common bus. When RRDENB is asserted, the selected device (selected by RXADDR[1:0]) drives these outputs, transferring the data to the upstream hardware.
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* Loopback The IDT77155 supports two loopback functions that are enabled by control bits in the control register. * Local Loopback The local loopback mode provides a connection within the PHY between transmit and receive data. This loopback connects the high speed transmit data and clock to the high speed receive data and clock as shown in Figure 9. Note that while this mode is operating, no data is forwarded to or received from the line interface. * Line Loopback The line loopback might also be called "remote loopback" since it provides for a means to test the overall system, including the line. The line loopback connects the high speed receive data and clock to the transmit data and clock as shown in Figure 10.
77155#1 "UTOPIA Transmit Bus" --TDAT[7:0] --TXPRTY --TSOC --TXADDR[1:0] TCA 12
Optical Transceiver
12 77155#2 12 77155#3 12 77155#4 Optical Transceiver
77155 drw 12
Optical Transceiver
Optical Transceiver
"Upstream" Hardware
Figure 7. Multi-PHY: Transmit Direction
12 77155#1 "UTOPIA Receive Bus" --RDAT[7:0] --RXPRTY --RSOC --RXADDR[1:0] RCA 12 Optical Transceiver
12 77155#2 12 77155#3 12 77155#4 Optical Transceiver
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Optical Transceiver
Optical Transceiver
"Upstream" Hardware
Figure 8. Multi-PHY: Receive Direction
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RATE1 RATE0 XOFF TGFC TCP TFPO
ADVANCED INFORMATION Commercial Temperature Range
ATP2 TBYP
TCLK
TRCLKTFCLK timsnarT MTA lleC OFIF TXPRTY TDAT[7:0] TSOC TCA TxADDR[1:0] MPHYEN RxADDR[1:0] TSEN RFCLK RXPRTY RDAT[7:0] RSOC RCA Transmit UTOPIA Cell FIFO Transmit SONET Framer Parallel to Serial Clk Gen. TRCLK+ TXCTXC+ redocnE Encoder TXD+ TXDRXDORXDReceive UTOPIA Cell FIFO Decoder Receive SONET Framer Serial to Parallel Clk Rec. Micoprocessor Interface .ceR klC RXD+ RXDO+ RRCLKRRCLK+ ALOSALOS+
ALE A[7:0] D[7:0]
LFO LF- LF+ APT1
RST
RFP
RCP RGFC
RALM
RBYP
RCLK
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Figure 9. Local Loopback
RATE1 RATE0 XOFF TGFC TCP TFPO TCLK ATP2 TBYP
TRCLKTFCLK timsnarT MTA lleC OFIF TXPRTY TDAT[7:0] TSOC TCA TxADDR[1:0] MPHYEN RxADDR[1:0] TSEN RFCLK RXPRTY RDAT[7:0] RSOC RCA Transmit UTOPIA Cell FIFO Transmit SONET Framer Parallel to Serial Clk Gen. TRCLK+ TXCTXC+ redocnE RBYP .ceR klC
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Encoder
TXD+ TXDRXDORXD-
Receive UTOPIA Cell FIFO
Decoder Receive SONET Framer Serial to Parallel Clk Rec. Micoprocessor Interface
RXD+ RXDO+ RRCLKRRCLK+ ALOSALOS+
ALE A[7:0] D[7:0]
RCP RGFC
RALM
Figure 10. Line Loopback
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RCLK
LFO LF- LF+ APT1
RFP
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REGISTER LISTING
Address 0X00 0X01 0X02 0X04 0X05 0X06 0X07 0X10 0X11 0X12 0X13 0X14 0X15 0X18 0X19 0X1A 0X1B 0X1C 0X1D 0X1E 0X1F 0X20 0X21 0X24 0X25 0X26 0X27 0X30 0X31 0X33 0X37 0X38 0X39 0X3A 0X3B 0X3D Register Master Reset & ID Register Configuration Register Interrupt Register Master Clock Monitor Register Master Control Register Transmit Clock Synthesis Control/Status Register Receive Clock/Data Recovery Control/Stuts Register Receive Section Overhead Control Register Receive Section Overhead Status Register Receive Section BIP Error Counter (LSB) Receive Section BIP Error Counter (MSB) Transmit Section Overhead Control Register Transmit Section Overhead Control Register Receive Line Overhead Status Register Receive Line Overhead Interrupt Register Receive Line BIP Error Counter (LSB) Receive Line BIP Error Counter Receive Line BIP Error Counter (MSB) Receive Line FEBE Counter (LSB) Receive Line FEBE Counter Receive Line FEBE Counter (MSB) Transmit Line Overhead Stutus Register Transmit Line Overhead Control Register Transmit K1 Byte Register Transmit K2 Byte Register Receive K1 Byte Register Receive K2 Byte Register Receive Path Overhead Status Register Receive Path Overhead Interrupt Register Receive Path Overhead Interrupt Enable Register Receive Path Signal Lable Byte Register Receive Path BIP Error Counter (LSB) Receive Path BIP Error Counter (MSB) Receive Path FEBE Counter (LSB) Receive Path FEBE Counter (MSB) Receive Path BIP Error Control Register Address 0X40 0X41 0X45 0X46 0X48 0X49 0X50 0X51 0X52 0X53 0X54 0X55 0X56 0X57 0X58 0X59 0X5A 0X60 0X61 0X62 0X63 0X64 0X65 0X66 0X67 0X68 0X70 0X71 0X72 0X73 0X74 0X75 0X76 0X77 0X78 0X7F Register Transmit Path Overhead Control Register Tramsmit Pointer Control Register Transmit Pointer LSB Register Transmit Pointer MSB Register Transmit Path Signal Lable Byte Register Transmit Path Overhead Control Register Receive Cell Control Register Receive Cell Interrupts & Interrupt Enable Register Receive Cell Match Header Register Receive Cell Match Header Mask Register Receive Cell Correctable Error Counter Receive Cell Uncorrectable Error Counter Receive Cell Counter (LSB) Receive Cell Counter Receive Cell Counter (MSB) Receive Cell Configuration Register Receive ID Address Register Transmit Cell Control Register Transmit Cell Idle/Unassigned Cell Header Pattern Transmit Cell Idle/Unassigned Cell Header Pattern Transmit Cell Configuration Register Transmit Cell Counter (LSB) Transmit Cell Counter Transmit Cell Counter (MSB) Transmit Cell Configuration Register Transmit ID Address Register Receive BER Status/Control Register Receive BER Fail Threshold Register Receive BER Fail Window Register Receive BER Fail Denominator Register (LSB) Receive BER Fail Denominator Register (MSB) Receive BER Warning Threshold Register Receive BER Warning Window Register Receive BER Warning Denominator Register (LSB) Receive BER Warning Denominator Register (MSB) Output PECL Control Register
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CONFIGURATION, CONTROL AND STATUS REGISTERS
MASTER RESET & ID REGISTER ADDRESS 0X00
Bit Bit 7 Type R/W Symbol mstReset
DEFAULT = 8'B00110000
Function Software reset control. A logic one resets entire sonet digital logic, and a logic zero has to be written to clear software reset. It resets the whole chip into a low-power stand-by mode. A hardware reset sets the whole register to its default state. Type value for the identification of chip. Type value for the identification of chip. Type value for the identification of chip. Revision ID number. Revision ID number. Revision ID number. Revision ID number.
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R R R R R
type[2] type[1] type[0] id[3] id[2] id[1] id[0]
CONFIGURATION REGISTER ADDRESS 0X01
Bit Bit 7 Bit 6 Type -- R/W
DEFAULT = 8'B01110000
Symbol -- Reserved Controls assertion of far end block errors (FEBE) in the transmit stream upon detection of line and path error events. When set to logic one, path FEBE errors are inserted in the transmit stream for each line or path BIP error event in the receive stream. When deasserted, no such errors are inserted. Controls assertion of line remote defect indication (LRDI) upon detection of alarms. When set to a logic one, a line RDI is inserted into the transmit stream upon detection of LOS, LOF, or LAIS in the receive stream. Controls assertion of path remote defect indication (PRDI) upon detection of alarms. When set to a logic one, PRDI is inserted into the transmit stream upon detection of an LOS, LOF, LAIS, LOP, PAIS, or LOC signal. Select active polarity of TCA signal. Default is the TCA signal being active high. Select active polarity of RCA signal. Default is the RCA signal being active high. Select active polarity of the RXD+/- inputs. Default selects RXD+ to be active high and RXD- to be active low. Reserved Function
autoFEBE
Bit 5
R/W
autoLRDI
Bit 4
R/W
autoPRDI
Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W --
TCAInv RCAInv RXDInv --
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INTERRUPT REGISTER ADDRESS 0X02
Bit Bit 7 Type R
DEFAULT = 8'BXXXXXXXX
Symbol txOOLInt Function Transmit reference out of lock interrupt status indication. It indicates the transmit clock synthesis PLL is unable to lock to the reference frequency TRCLK+/-. This bit is cleared when the register is read. Asserted when the loss of cell delineation (LOC) signal changes state. This bit is reset after a read to this register. Receive data out of lock interrupt status indication. It indicates the receive clock/data recovery PLL's recovered clock is not within Bellcore's requirement of frequency variation with respect to the reference clock RRCLK+/-. It is also asserted if no transitions have occurred on the RXD+/- inputs for 80 bit periods. This bit is cleared when the register is read. Interrupt is asserted upon the detection of an interrupt from the tx cell delineation block. Interrupt is asserted upon the detection of an interrupt from the rx cell delineation block. Interrupt is asserted upon the detection of an interrupt from the rx path overhead section of the transmission convergence block. Interrupt is asserted upon the detection of an interrupt from the rx line overhead section of the transmission convergence block. Interrupt is asserted upon the detection of an interrupt from the rx section overhead section of the transmission convergence block.
Bit 6 Bit 5
R R
rxLOCInt rxOOLInt
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R R R
txCDi rxCDi rxPOHi rxLOHi rxSOHi
MASTER CLOCK MONITOR REGISTER ADDRESS 0X04
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type -- -- -- -- R R R R Symbol -- -- -- -- rrclkReg trclkReg rclkReg tclkReg
DEFAULT = 8'BXXXXXXXX
Function Reserved Reserved Reserved Reserved RRCLK+/- monitor. Set on the rising edge of RRCLK+/-. Cleared when this register is read. TRCLK+/- monitor. Set on the rising edge of TRCLK+/-. Cleared when this register is read. RCLK monitor. Set on the rising edge of the output clock RCLK. Cleared when this register is read. TCLK monitor. Set on the rising edge of the output clock TCLK. Cleared when this register is read.
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IIDT77155 155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
ADVANCED INFORMATION Commercial Temperature Range
MASTER CONTROL REGISTER ADDRESS 0X05
Bit Bit 7 Type R/W Symbol rxLOCIEn
DEFAULT = 8'B00100000
Function Loss of cell delineation interrupt enable. When set to a logic one, the INTB signal of the chip is asserted when a change in the LOC signal occurs. Loss of cell delineation (LOC) indication. Set payload pointer at 522 and disable any pointer movement. (Default = 1) Reserved Reserved Line loopback enable. When a logic one, TXD+/- are connected internally to RXD+/-. Diagnostic loopback enable. The serial output and clock streams are connected internally to the serial input streams. Loop time operation enable. When a logic one, the transmitter clock is the recovered receive clock when RBYP is disabled, or RRCLK+/- when RBYP is asserted. By default, the transmit clock is derived from TRCLK+/-.
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R/W -- -- R/W R/W R/W
LOC txFixptr -- -- txLLoop rxDLoop rxLoopT
TRANSMIT CLOCK SYNTHESIS CONTROL/STATUS REGISTER ADDRESS 0X06
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type -- -- -- -- R -- R/W R/W Symbol -- -- -- -- txOOL -- txOOLIEn txrefSel Reserved Reserved Reserved Reserved
DEFAULT = 8'B0000X000
Function
Transmit out of lock status signal indicating the transmit clock synthesis logic is unable to lock to the reference clock TRCLK+/-. Reserved Interrupt enable for the transmit out of lock indication. Selects the expected frequency of TRCLK+/-. If a logic 0, the reference frequency is 19.44 MHz, else the reference frequency must be 6.48 MHz. It affects the clock synthesis frequency only when TBYP is deasserted.
RECEIVE CLOCK/DATA RECOVERY CONTROL/STATUS REGISTER ADDRESS 0X07
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Type -- -- -- -- R Symbol -- -- -- -- rxOOL Reserved Reserved Reserved Reserved Function
DEFAULT = 8'B0000X000
Receive out of lock status signal indicating the receive clock/data recovery logic is unable to lock to the input data stream. It is asserted if the recovered clock is not within 244ppm of the reference clock RRCLK+/- or if there are no transitions on the RXD+/- inputs for 80n bit periods. Reserved Interrupt enable for the receive out of lock indication. Selects the expected frequency of RRCLK+/-. If a logic 0, the reference frequency is 19.44 MHz, else the reference frequency must be 6.48 MHz. It affects the clock/data recovery logic frequency only when RBYP is deasserted.
Bit 2 Bit 1 Bit 0
-- R/W R/W
-- rxOOLIEn rxrefSel
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IDT77155 155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
ADVANCED INFORMATION Commercial Temperature Range
RECEIVE SECTION OVERHEAD CONTROL REGISTER ADDRESS 0X10
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type -- R/W W -- R/W R/W R/W R/W Symbol -- scrDis frcOOF -- B1ErrIEn LOSIEn LOFIEn OOFIEn Reserved
DEFAULT = 8'B00000000
Function
Disable receive frame scrambler if set to logic one. When set to logic one, the receive section overhead logic is forced out of frame at the next frame boundary. Reserved Interrupt enable for rx section BIP (B1) error. When asserted, an interrupt is generated if section BIP (B1) error is detected. Receive loss of signal interrupt enable. When asserted, an interrupt is generated if LOS alarm changes state. Receive loss of frame interrupt enable. When set to logic one, an interrupt is generated if LOF alarm changes state. Receive out of frame interrupt enable. When set to logic one, an interrupt is generated if OOF alarm changes state.
RECEIVE SECTION OVERHEAD STATUS REGISTER ADDRESS 0X11
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Symbol C1Int B1ErrInt LOSInt LOFInt OOFInt LOS LOF OOF
DEFAULT = 8'BXXXXXXXX
Function
Interrupt bit set if received C1 bytes received do not correspond to 1, 2, 3 respectively. This bit is cleared when this register is read. Interrupt is asserted if section BIP (B1) errors received. This bit is cleared when this register is read. Loss of signal interrupt is asserted if LOS changes state. This bit is cleared when this register is read. Loss of frame interrupt is asserted if LOF changes state. This bit is cleared when this register is read. Out of frame interrupt is asserted if OOF changes state. This bit is cleared when this register is read. Loss of signal status indication. Asserted high. Loss of frame status indication. Asserted high. Out of frame status indication. Asserted high.
RECEIVE SECTION BIP ERROR COUNTER DEFAULT = 16'HXXXX ADDRESS 0X12
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Symbol B1ErrCnt[7] B1ErrCnt[6] B1ErrCnt[5] B1ErrCnt[4] B1ErrCnt[3] B1ErrCnt[2] B1ErrCnt[1] B1ErrCnt[0] Function B1 error counter bit B1 error counter bit B1 error counter bit B1 error counter bit B1 error counter bit B1 error counter bit B1 error counter bit B1 error counter bit
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IIDT77155 155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
ADVANCED INFORMATION Commercial Temperature Range
ADDRESS 0X13
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Symbol B1ErrCnt[15] B1ErrCnt[14] B1ErrCnt[13] B1ErrCnt[12] B1ErrCnt[11] B1ErrCnt[10] B1ErrCnt[9] B1ErrCnt[8] Function B1 error counter bit B1 error counter bit B1 error counter bit B1 error counter bit B1 error counter bit B1 error counter bit B1 error counter bit B1 error counter bit
NOTE: 1. B1ErrCnt[15:0] Receive section overhead BIP (B1) error counter. Cumulative error counter keeping track of errors from the previous poll of these registers. The error count is polled by writing to either register or to address `h00. Such a write transfers accumulated errors to a holding register which may be read later, and the registers are cleared. This transfer and reset of the registers are done such that coincident events are not lost. All error registers in the receive sections of the transmission convergence block or the cell delineation block may be polled by a write to the master register `h00.
TRANSMIT SECTION OVERHEAD CONTROL REGISTER ADDRESS 0X14
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type -- R/W -- -- -- -- -- R/W Symbol -- scrDis -- -- -- -- -- LAISIns Reserved
DEFAULT = 8'B00000000
Function
Disable transmit frame scrambler. Scrambling enabled if logic zero. Reserved Reserved Reserved Reserved Reserved Insert line alarm signal (LAIS) in transmit stream. Line alarm results in all bits except the section overhead bytes being set to logic 1 prior to scrambling.
TRANSMIT SECTION OVERHEAD CONTROL REGISTER ADDRESS 0X15
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type -- -- -- -- -- R/W R/W R/W Symbol -- -- -- -- -- LOSIns B1Inv frErrIns Reserved Reserved Reserved Reserved Reserved
DEFAULT = 8'B00000000
Function
Insert loss of signal into transmit stream. The transmit stream is forced to all zeroes if this bit is asserted. Invert B1 byte before insertion into transmit stream. controls error insertion into the section B1 byte. Insert framing error. Inserts a single bit error continuously into the most significant bit of the A1 section overhead byte. When this bit is set to logic one, the A1 bytes transmitted are 0x76 instead of 0xf6.
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IDT77155 155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
ADVANCED INFORMATION Commercial Temperature Range
RECEIVE LINE OVERHEAD STATUS REGISTER ADDRESS 0X18
Bit Bit 7 Type R/W Symbol B2Word
DEFAULT = 8'B00000000
Function
Controls accumulation of B2 errors. If set to logic one, the B2 error counter is incremented only once per frame for one or more errors received during that frame. When disabled, the B2 error counter is incremented by the received error count during that frame. Max B2 errors is 8 per frame for STS-1 and 24 for STS-3c per frame. Reserved Reserved Reserved Reserved Reserved Receive line alarm signal status indication. Receive line remote defect indication status indication.
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
-- -- -- -- -- R R
-- -- -- -- -- LAIS LRDI
RECEIVE LINE OVERHEAD INTERRUPT REGISTER ADDRESS 0X19
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R R R R Symbol LFEBEIEn B2ErrIEn LAISIEn LRDIIEn LFEBEInt B2ErrInt LAISInt LRDIInt
DEFAULT = 8'B0000XXXX
Function
Receive line FEBE (Z2) error interrupt enable. If set to logic one, an interrupt is generated if a line FEBE is detected. Receive line BIP (B2) error interrupt enable. If set to logic one, an interrupt is generated if a line BIP (B2) error is detected. Receive line alarm indication signal interrupt enable. If set to logic one, an interrupt is generated if LAIS changes state. Receive line RDI error interrupt enable. If set to logic one, an interrupt is generated if line RDI signal changes state. Receive line FEBE (Z2) error interrupt is asserted when a line FEBE is detected. Cleared when this register is read. Receive line BIP error interrupt is asserted when a B2 error is detected. Cleared when this register is read. Receive line alarm interrupt is asserted when a change in the line alarm signal (LAIS) occurs. Cleared when this register is read. Receive line RDI interrupt is asserted when a change in the line RDI signal occurs. Cleared when this register is read.
RECEIVE LINE OVERHEAD BIP ERROR COUNTER DEFAULT = 20'HXXXXX ADDRESS 0X1A
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Symbol B2ErrCnt[7] B2ErrCnt[6] B2ErrCnt[5] B2ErrCnt[4] B2ErrCnt[3] B2ErrCnt[2] B2ErrCnt[1] B2ErrCnt[0] Function B2 error counter bit B2 error counter bit B2 error counter bit B2 error counter bit B2 error counter bit B2 error counter bit B2 error counter bit B2 error counter bit
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IIDT77155 155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
ADVANCED INFORMATION Commercial Temperature Range
ADDRESS 0X1B
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Symbol B2ErrCnt[15] B2ErrCnt[14] B2ErrCnt[13] B2ErrCnt[12] B2ErrCnt[11] B2ErrCnt[10] B2ErrCnt[9] B2ErrCnt[8] Function B2 error counter bit B2 error counter bit B2 error counter bit B2 error counter bit B2 error counter bit B2 error counter bit B2 error counter bit B2 error counter bit
ADDRESS 0X1E
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Symbol FEBECnt[15] FEBECnt[14] FEBECnt[13] FEBECnt[12] FEBECnt[11] FEBECnt[10] FEBECnt[9] FEBECnt[8] Function FEBE counter bit FEBE counter bit FEBE counter bit FEBE counter bit FEBE counter bit FEBE counter bit FEBE counter bit FEBE counter bit
ADDRESS 0X1C
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type -- -- -- -- R R R R Symbol -- -- -- -- B2ErrCnt[19] B2ErrCnt[18] B2ErrCnt[17] B2ErrCnt[16] Function Reserved Reserved Reserved Reserved B2 error counter bit B2 error counter bit B2 error counter bit B2 error counter bit
ADDRESS 0X1F
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type -- -- -- -- R R R R Symbol -- -- -- -- FEBECnt[19] FEBECnt[18] FEBECnt[17] FEBECnt[16] Function Reserved Reserved Reserved Reserved FEBE counter bit FEBE counter bit FEBE counter bit FEBE counter bit
NOTE: 1. B2ErrCnt[19:0] BIP error counter of the receive line overhead section (B2 errors). Cumulative error counter keeping track of errors from the previous poll of these registers. The error count is polled by writing to either of the registers, or either of the Z2 error registers, or to address `h00. Such a write transfers accumulated errors to a holding register which may be read later, and the registers are cleared. This transfer and reset of the registers are done such that coincident events are not lost. All error registers in the receive sections of the transmission convergence block or the cell delineation block may be polled by a write to the master register `h00.
NOTE: 1. FEBECnt[19:0] FEBE (Far End Block Error in receive Z2) counter of the receive line overhead section. Cumulative error counter keeping track of errors from the previous poll of these registers. The error count is polled by writing to either of the registers, or either of the B2 error registers, or to address `h00. Such a write transfers accumulated errors to a holding register which may be read later, and the registers are cleared. This transfer and reset of the registers are done such that coincident events are not lost. All error registers in the receive sections of the transmission convergence block or the cell delineation block may be polled by a write to the master register `h00
RECEIVE LINE FEBE COUNTER DEFAULT = 20'HXXXXX ADDRESS 0X1D
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Symbol FEBECnt[7] FEBECnt[6] FEBECnt[5] FEBECnt[4] FEBECnt[3] FEBECnt[2] FEBECnt[1] FEBECnt[0] Function FEBE counter bit FEBE counter bit FEBE counter bit FEBE counter bit FEBE counter bit FEBE counter bit FEBE counter bit FEBE counter bit
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IDT77155 155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
ADVANCED INFORMATION Commercial Temperature Range
TRANSMIT LINE OVERHEAD STATUS REGISTER DEFAULT = 8'B00000000 ADDRESS 0X20
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type -- -- -- -- -- -- -- R/W Symbol -- -- -- -- -- -- -- LRDI Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Transmit line RDI insertion into transmit stream. When set to logic one, line RDI is inserted by transmitting the code 110 into the 3 least significant bits of the K2 byte of the transmit stream.
TRANSMIT K2 BYTE REGISTER DEFAULT = 8'B00000000 ADDRESS 0X25
Bit Bit 7 Bit 6 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W Symbol K2Ins[7] K2Ins[5] K2Ins[4] K2Ins[3] K2Ins[2] K2Ins[1] K2Ins[0] Function K2 Insertion Bit 7 K2 Insertion Bit 5 K2 Insertion Bit 4 K2 Insertion Bit 3 K2 Insertion Bit 2 K2 Insertion Bit 1 K2 Insertion Bit 0
NOTE: 1. k2Ins[7:0] Value to be inserted into the K2 byte of transmit stream. Continuously inserts this value into the transmit stream. However, the least significant 4 bits of the K2 byte in the transmit stream is overridden by the path RDI value and the line FERF value if error conditions are detected in the receive section of the transmission convergence logic.
TRANSMIT LINE OVERHEAD CONTROL REGISTER DEFAULT = 8'B00000000 ADDRESS 0X21
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type -- -- -- -- -- -- -- R/W Symbol -- -- -- -- -- -- -- B2Inv Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved When set to logic one, B2 byte is inverted before insertion into transmit stream.
RECEIVE K1 BYTE REGISTER DEFAULT = 8'BXXXXXXXX ADDRESS 0X26
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Symbol K1[7] K1[6] K1[5] K1[4] K1[3] K1[2] K1[1] K1[0] Function Receive K1 Bit 7 Receive K1 Bit 6 Receive K1 Bit 5 Receive K1 Bit 4 Receive K1 Bit 3 Receive K1 Bit 2 Receive K1 Bit 1 Receive K1 Bit 0
NOTE: 1. k1[7:0] K1 byte of receive stream. Updated if new K1 byte received for 3 consecutive frames.
TRANSMIT K1 BYTE REGISTER DEFAULT = 8'B00000000 ADDRESS 0X24
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Symbol K1Ins[7] K1Ins[6] K1Ins[5] K1Ins[4] K1Ins[3] K1Ins[2] K1Ins[1] K1Ins[0] Function K1 Insertion Bit 7 K1 Insertion Bit 6 K1 Insertion Bit 5 K1 Insertion Bit 4 K1 Insertion Bit 3 K1 Insertion Bit 2 K1 Insertion Bit 1 K1 Insertion Bit 0
RECEIVE K2 BYTE REGISTER DEFAULT = 8'BXXXXXXXX ADDRESS 0X27
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Symbol K2[7] K2[6] K2[5] K2[4] K2[3] K2[2] K2[1] K2[0] Function Receive K2 Bit 7 Receive K2 Bit 6 Receive K2 Bit 5 Receive K2 Bit 4 Receive K2 Bit 3 Receive K2 Bit 2 Receive K2 Bit 1 Receive K2 Bit 0
NOTE: 1. k1Ins[7:0] Value to be inserted into the K1 byte of transmit stream. Continuously inserts this value into the transmit stream. 8.03
NOTE: 1. k2[7:0] K2 byte of receive stream. Updated if new K2 byte received for 3 consecutive frames 26
IIDT77155 155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
ADVANCED INFORMATION Commercial Temperature Range
RECEIVE PATH OVERHEAD STATUS REGISTER ADDRESS 0X30
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type -- -- R -- R R -- -- Symbol -- -- LOP -- PAIS PRDI -- --
DEFAULT = 8'B00X0XX00
Function
Reserved Reserved Receive loss of pointer (LOP) status indication. Reserved Receive path alarm indication (PAIS) status signal. Receive path remote path indication status indication. Reserved Reserved
RECEIVE PATH OVERHEAD INTERRUPT REGISTER ADDRESS 0X31
Bit Bit 7 Type R Symbol C2Int
DEFAULT = 8'BX0X0XXXX
Function
C2 label bytes error interrupt. Asserted when the expected C2 value is not received for 5 consecutive frames. The C2byte register (`h37) stores the most recently received C2 byte. Reserved Loss of pointer interrupt et when a change in LOP signal occurs. Cleared when this register is read. Reserved Path alarm indication signal interrupt is asserted when a change in the PAIS signal occurs. Cleared when this register is read. Path RDI interrupt is asserted when a change in the path RDI signal occurs. Cleared when this register is read. Path BIP (B3) error interrupt is asserted when a path BIP (B3) error is detected. Cleared when this register is read. Path FEBE (bit 1-4 of G1) interrupt is asserted when a path FEBE is detected. Cleared when this register is read.
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
-- R -- R R R R
-- LOPInt -- PAISInt PRDIInt B3ErrInt PFEBEInt
RECEIVE PATH OVERHEAD INTERRUPT ENABLE REGISTER ADDRESS 0X33
Bit Bit 7 Type R/W Symbol C2IEn Function
DEFAULT = 8'B00000000
C2 signal label bytes error interrupt enable If set to logic one, an interrupt is generated if a C2 error is detected. C2 error occurs when unexpected C2 bytes are received for 5 consecutive frames. Reserved Loss of pointer interrupt enable. If set to logic one, an interrupt is generated if a LOP change is detected. Reserved Path alarm indication signal interrupt enable. If set to logic one, an interrupt is generated if a PAIS change is detected. Path RDI interrupt enable. If set to logic one, an interrupt is generated if a path RDI change is detected. Path BIP (B3) error interrupt enable. If set to logic one, an interrupt is generated if a path BIP (B3) error is detected. Path FEBE (bit 1-4 of G1) interrupt enable. If set to logic one, an interrupt is generated if a path FEBE is detected.
Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 Bit 0
-- R/W -- R/W R/W R/W R/W
-- LOPIEn -- PAISIEn PRDIIEn B3ErrIEn PFEBEIEn
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IDT77155 155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
ADVANCED INFORMATION Commercial Temperature Range
RECEIVE PATH SIGNAL LABEL BYTE REGISTER DEFAULT = 8'BXXXXXXXX ADDRESS 0X37
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Symbol C2rx[7] C2rx[6] C2rx[5] C2rx[4] C2rx[3] C2rx[2] C2rx[1] C2rx[0] Function Receive C2 Bit 7 Receive C2 Bit 6 Receive C2 Bit 5 Receive C2 Bit 4 Receive C2 Bit 3 Receive C2 Bit 2 Receive C2 Bit 1 Receive C2 Bit 0
RECEIVE PATH FEBE COUNTER DEFAULT = 16'HXXXX ADDRESS 0X3A
Bit Bit 7 Bit 6 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R Symbol PFEBECnt[7] PFEBECnt[5] PFEBECnt[4] PFEBECnt[3] PFEBECnt[2] PFEBECnt[1] PFEBECnt[0] Function Path FEBE counter bit Path FEBE counter bit Path FEBE counter bit Path FEBE counter bit Path FEBE counter bit Path FEBE counter bit Path FEBE counter bit
NOTE: 1. C2rx[7:0] most recent errored path label byte received which led to the C2 interrupt.
ADDRESS 0X3B
Bit Bit 7 Type R R R R R R R R Symbol PFEBECnt[15] PFEBECnt[14] PFEBECnt[13] PFEBECnt[12] PFEBECnt[11] PFEBECnt[10] PFEBECnt[9] PFEBECnt[8] Function Path FEBE counter bit Path FEBE counter bit Path FEBE counter bit Path FEBE counter bit Path FEBE counter bit Path FEBE counter bit Path FEBE counter bit Path FEBE counter bit
RECEIVE PATH OVERHEAD BIP ERROR COUNTER DEFAULT = 16'HXXXX ADDRESS 0X38
Bit Bit 7 Bit 6 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R Symbol B3ErrCnt[7] B3ErrCnt[5] B3ErrCnt[4] B3ErrCnt[3] B3ErrCnt[2] B3ErrCnt[1] B3ErrCnt[0] Function B3 error counter bit B3 error counter bit B3 error counter bit B3 error counter bit B3 error counter bit B3 error counter bit B3 error counter bit
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ADDRESS 0X39
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Symbol B3ErrCnt[15] B3ErrCnt[14] B3ErrCnt[13] B3ErrCnt[12] B3ErrCnt[11] B3ErrCnt[10] B3ErrCnt[9] B3ErrCnt[8] Function B3 error counter bit B3 error counter bit B3 error counter bit B3 error counter bit B3 error counter bit B3 error counter bit B3 error counter bit B3 error counter bit
NOTE: 1. PFEBECnt[15:0] Receive path FEBE (Bit 1-4 of G1 byte) counter. Cumulative error counter keeping track of errors from the previous poll of these registers. The error count is polled by writing to either of the registers, or either of the BIP (B3) error registers, or to address `h00. Such a write transfers accumulated errors to a holding register which may be read later, and the registers are cleared. This transfer and reset of the registers are done such that coincident events are not lost. All error registers in the receive sections of the transmission convergence block or the cell delineation block may be polled by a write to the master register`h00.
NOTE: 1. B3ErrCnt Receive path overhead BIP (B3) error counter. Cumulative error counter keeping track of errors from the previous poll of these registers. The error count is polled by writing to either of the registers, or either of the RDI error registers, or to address `h00. Such a write transfers accumulated errors to a holding register which may be read later, and the registers are cleared. This transfer and reset of the registers are done such that coincident events are not lost. All error registers in the receive sections of the transmission convergence block or the cell delineation block may be polled by a write to the master register `h00
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IIDT77155 155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
ADVANCED INFORMATION Commercial Temperature Range
RECEIVE PATH BIP ERROR CONTROL REGISTER ADDRESS 0X3D
Bit Bit 7 Bit 6 Bit 5 Type -- -- R/W Symbol -- -- blkBIP Function Reserved Reserved
DEFAULT = 8'B00000000
Controls accumulation of B3 errors. If set to logic one, the B3 error counter is incremented only once per SPE for one or more errors received during that frame. When disabled, the B3 error counter is incremented by the received error count during that SPE. Max B3 errors is 8 per SPE. Reserved Reserved Reserved Reserved Reserved
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
-- -- -- -- --
-- -- -- -- --
TRANSMIT PATH OVERHEAD CONTROL REGISTER ADDRESS 0X40
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Type -- -- -- -- -- -- R/W Symbol -- -- -- -- -- -- B3Inv Reserved Reserved Reserved Reserved Reserved Reserved
DEFAULT = 8'B00000000
Function
Invert B3 byte before insertion into the transmission stream. When set to a logic one, the B3 byte is inverted causing the insertion of 8 BIP errors per frame. The B3 byte is uncorrupted when this bit is a logic zero. Insert path alarm indication signal into the transmit stream. When a logic one, the complete SPE, and the pointer bytes (H1, H2, & H3) are overwritten with the all ones pattern.
Bit 0
R/W
PAISIns
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IDT77155 155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
ADVANCED INFORMATION Commercial Temperature Range
TRANSMIT POINTER CONTROL REGISTER ADDRESS 0X41
Bit Bit 7 Bit 6 Type -- R/W Symbol -- frcPtr
DEFAULT = 8'B00000000
Function Reserved Force the insertion of the pointer values (H1 & H2 bytes) in the pointer registers (`h45, `h46) into the transmit stream for diagnostics. The SPE and other overheads are transmitted in a normal fashion although it would not be extracted by the receiving logic due to an incorrect pointer. At least one corrupted pointer is guaranteed to be sent. Stuff opportunity spacing between consecutive SPE stuff events. When asserted to a logic one, stuff events controlled by incPtr and decPtr is generated at a maximum rate of once every four frames. Else, stuff events may be generated every frame. Initialize pointer value of next frame with pointer value contained in `h45 and `h46. The registers at `h45 and `h46 are initialized before this bit is set to a logic one. If a legal pointer value is loaded (0 <= pointer <= 782) then the transmit pointer value is changed to this value with the SPE being modified to this position appropriately. This bit is cleared once the new pointer is loaded. Controls insertion of the new data flags in `h46 into the transmit stream. When asserted to a logic one, the pattern in `h46 is inserted continuously in the payload pointer. When disabled, the normal pointer value (`b0110) is inserted. Decrement pointer in the next immediate frame. This bit is cleared when the new pointer value is inserted in the transmit stream. This bit has no effect if the transmit fixPtr bit is asserted. Increment pointer in the next immediate stream. This bit is cleared when the new pointer value is inserted in the transmit stream. This bit has no effect if the transmit fixPtr bit is asserted. Reserved
Bit 5
R/W
stuffCtl
Bit 4
R/W
Ptr
Bit 3
R/W
NDF
Bit 2
R/W
decPtr
Bit 1
R/W
incPtr
Bit 7
--
--
TRANSMIT POINTER LSB REGISTER DEFAULT = 8'B00000000 ADDRESS 0X45
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R R R R R R R Symbol arbPtr[7] arbPtr[6] arbPtr[5] arbPtr[4] arbPtr[3] arbPtr[2] arbPtr1] arbPtr[0] Function Arbitrary pointer Bit 7 Arbitrary pointer Bit 6 Arbitrary pointer Bit 5 Arbitrary pointer Bit 4 Arbitrary pointer Bit 3 Arbitrary pointer Bit 2 Arbitrary pointer Bit 1 Arbitrary pointer Bit 0
NOTE: 1. arbPtr[7:0] Payload pointer to be inserted into frame if Ptr is set. A legal value results in the transmit payload pointer changing to the corresponding byte position. If the frcPtr bit is set, the payload pointer changes to this arbitrary value but the SPE position remains unchanged.
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IIDT77155 155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
ADVANCED INFORMATION Commercial Temperature Range
TRANSMIT POINTER MSB REGISTER ADDRESS 0X46
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Type R/W R/W R/W R/W R/W Symbol NDFVal[3] NDFVal[2] NDFVal[1] NDFVal[0] ssBit[1]
DEFAULT = 8'B10010000
Function New data flag field value to be inserted into the transmit stream if ldPtr is set or if NDF bit is set.
SONET/SDH switch bit and ss bits value of the transmit stream. If ssBit[1] is a logic high, then the chip transforms to full SDH mode. By default (ssBit[1] = `0'), the chip follows the SONET specifications. SONET mode: ssBit[1] = `0' (1) ss bits of pointer is set to "00" for transmit direction. (2) Line AIS detection criteria. AIS-L enter state: 5 consecutive frames with "111" in bits 6-8 of K2 byte are detected. AIS-L exit state: 5 consecutive frames with pattern other than "111" in bits 6-8 of K2 byte are detected. (3) Line RDI detection criteria. RDI-L enter state: 5 consecutive frames with "110" in bits 6-8 of K2 byte are detected. RDI-L exit state: 5 consecutive frames with pattern other than "110" in bits 6-8 of K2 byte are detected. (4) Path BIP-8 calculation for STS-1 applications Count 87 columns of SPE including 2 fixed stuffs column (column 30 and 59). (5) No consequent actions Line RDI for transmit direction by detection of B2 EBER (refer to register address `h70 BERfail) SDH mode: ssBit[1] = `1' (1) ss bits of pointer is set to "10" for transmit direction. (2) Line AIS detection criteria. AIS-L enter state: 3 consecutive frames with "111" in bits 6-8 of K2 byte are detected. AIS-L exit state: 3 consecutive frames with pattern other than "111" in bits 6-8 of K2 byte are detected. (3) Line RDI detection criteria. RDI-L enter state: 3 consecutive frames with "110" in bits 6-8 of K2 byte are detected. RDI-L exit state: 3 consecutive frames with pattern other than "110" in bits 6-8 of K2 byte are detected. (4) Path BIP-8 calculation for STS-1 applications Count 85 columns of SPE excluding 2 fixed stuffs column (column 30 and 59). (5) Generate consequent actions Line RDI for transmit direction by detection of B2 EBER (refer to register address `h70 BERfail)
Bit 2 Bit 1
R/W R/W
ssBit[0] arbPtr[9]
ss bits value of the transmit stream. ssBit[0] is set to `0'.
most significant bits of the arbitrary payload pointer to be inserted into frame if ldPtr is set. A legal value results in the transmit payload pointer changing to the corresponding byte position. If the frcPtr bit is set, the payload pointer changes to this arbitrary value but the SPE position remains unchanged.
Bit 0
R/W
arbPtr[8]
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IDT77155 155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
ADVANCED INFORMATION Commercial Temperature Range
TRANSMIT PATH SIGNAL LABLE BYTE REGISTER DEFAULT = 8'B00010011 ADDRESS 0X48
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Symbol C2tr[7] C2tr[6] C2tr[5] C2tr[4] C2tr[3] C2tr[2] C2tr[1] C2tr[0] Function Transmit C2 Bit 7 Transmit C2 Bit 6 Transmit C2 Bit 5 Transmit C2 Bit 4 Transmit C2 Bit 3 Transmit C2 Bit 2 Transmit C2 Bit 1 Transmit C2 Bit 0
NOTE: 1. C2tr[7:0]C2 value to be inserted into the transmit stream. Default value is `h13 for ATM applications. Value may be changed for diagnostics purposes.
TRANSMIT PATH OVERHEAD CONTROL REGISTER ADDRESS 0X49
Bit Bit 7 Type R/W Symbol PFEBEIns[3]
DEFAULT = 8'B00000000
Function
Insert FEBE value into path status byte. This value is cleared after it has been inserted into the path status byte for transmission. Any non-zero value overrides the accumulated error values during the previous received frame. If a non-zero value is read from this register, it implies that the transmission is still pending.
Bit 6 Bit 5 Bit 4 Bit 3
R/W R/W R/W R/W
PFEBEIns[2] PFEBEIns[1] PFEBEIns[0] PRDIIns Insert path remote defect indication into transmit stream. When set to a logic one, the PRDI bit in the status byte is asserted. Once a PRDI indication is sent, it is guaranteed to be sent asserted for 10 consecutive frames. G1 bits to be inserted into path status byte least significant bits.
Bit 2 Bit 2 Bit 2
R/W R/W R/W
G1Ins[2] G1Ins[1] G1Ins[0]
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RECEIVE CELL CONTROL REGISTER ADDRESS 0X50
Bit Bit 7 Bit 6 Bit 5 Type R R/W R/W Symbol OCD parity pass
DEFAULT = 8'B00000100
Function Out of cell delineation status indication. When asserted high, the cell delineation state machine is in the hunt or presync state. Select odd or even parity for RXPRTY output. When set to logic one, it is even parity over the outputs RDAT[7:0], else it is odd parity. When enabled, filtering of cells with matching the pattern in cell header register `h52 masked with the mask register `h53 is disabled. Filtering of field with VPI = VCI = 0 is ignored and all cells are passed to the ATM layer. Disables the HEC error correction algorithm. any error detected in the incoming cell is treated as an uncorrectable error, and the cell is dropped. Controls the dropping of cells when an incorrectable HEC error is detected. When disabled, cells with uncorrectable errors are dropped. However, when set to a logic one, cells are passed to the TM layer regardless of the errors detected. The HEC verification state machine is always in the correction mode. cells are always dropped when the cell delineation state machine is in the hunt or presync states. Controls the addition of the coset polynomial. When a logic one, the coset polynomial is added to the header prior to comparison. Controls the descrambling of the cell payload. When asserted high, payload scrambling is disabled. Reset rx FIFO. Used to reset the four cell receive FIFO when asserted to a logic one.The FIFO ignores all writes until this bit is cleared.
Bit 4 Bit 3
R/W R/W
corDis HECdis
Bit 2 Bit 1 Bit 0
R/W R/W R/W
csetAdd scrDis rxFIFOrst
RECEIVE CELL INTERRUPTS & INTERRUPT ENABLE REGISTER ADDRESS 0X51
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R R R R -- Symbol OCDIEn HECIEn ovfIEn OCDInt corInt uncorInt ovfInt --
DEFAULT = 8'B000XXXX0
Function Out of cell delineation interrupt enable. If set to logic one, an interrupt is generated if an OCD change is detected Correctable or incorrectable HEC error interrupt enable. If set to logic one, an interrupt is generated if a correctable or uncorrectable error is detected FIFO overflow interrupt enable. If set to logic one, an interrupt is generated if a FIFO overrun is detected Out of cell delineation interrupt. Set when the OCD signal changes value. This bit is cleared following a read to this register. Correctable HEC error interrupt is asserted when a correctable HEC error is detected. This bit is cleared following a read to this register. Uncorrectable HEC error interrupt is asserted when an uncorrectable HEC error is detected. This bit is cleared following a read to this register. FIFO overflow interrupt is asserted when a receive FIFO overflow occurs. This bit is cleared following a read to this register. Reserved
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IDT77155 155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
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RECEIVE CELL MATCH HEADER REGISTER ADDRESS 0X52
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Symbol GFC[3] GFC[2] GFC[1] GFC[0] PTI[2] PTI[1] PTI[0] CLP
DEFAULT = 8'B00000000
Function GFC Bit 3 to match GFC of receive header GFC Bit 2 to match GFC of receive header GFC Bit 1 to match GFC of receive header GFC Bit 0 to match GFC of receive header PTI Bit 2 to match PTI of receive header PTI Bit 1 to match PTI of receive header PTI Bit 0 to match PTI of receive header CLP value to match CLP of receive header
NOTE: 1. GFC[3:0], PTI[2:0], CLPMatch header pattern to match in the GFC, PTI, & CLP portion of the received header. Cells matching the unmasked bits of this pattern, along with the criteria of VPI = VCI = 0, will be dropped. The receive pass bit control must be disabled to enable the dropping of idle/unassigned cells.
RECEIVE CELL MATCH HEADER MASK REGISTER ADDRESS 0X53
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Symbol GFCmsk[3] GFCmsk[2] GFCmsk[1] GFCmsk[0] PTImsk[2] PTImsk[1] PTImsk[0] CLPmsk Function Mask GFC Bit 3 Mask GFC Bit 2 Mask GFC Bit 1 Mask GFC Bit 0 Mask PTI Bit 2 Mask PTI Bit 1 Mask PTI Bit 0 Mask CLP
DEFAULT = 8'B00000000
NOTE: 1. GFCmsk[3:0], PTImsk[2:0], CLPmsk Mask bits for GFC, PTI, & CLP portion of the match header pattern. Cells matching the unmasked bits of the header pattern register (`h52) will be dropped. A logic one in any bit position enables the corresponding bit in the pattern register to be compared. Note that the VPI and VCI bits do not have a mask register. The pattern in them have to be a logic zero.
RECEIVE CELL CORRECTABLE ERROR COUNTER ADDRESS 0X54
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Symbol corCnt[7] corCnt[6] corCnt[5] corCnt[4] corCnt[3] corCnt[2] corCnt[1] corCnt[0] Function
DEFAULT = 8'BXXXXXXXX
Correctable HEC error count bit Correctable HEC error count bit Correctable HEC error count bit Correctable HEC error count bit Correctable HEC error count bit Correctable HEC error count bit Correctable HEC error count bit Correctable HEC error count bit
NOTE: 1. corCnt [7:0] Correctable HEC error count register. This is a cumulative error counter keeping track of errors from the previous poll of these registers. The error count is polled by writing to either of the HEC error registers (`h54 or `h55), or to address `h00. Such a write transfers accumulated errors to a holding register which may be read later, and the registers are cleared. This transfer and reset of the registers are done such that coincident events are not lost. All error registers in the receive sections of the transmission convergence block or the cell delineation block may be polled by a write to the master register `h00.
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RECEIVE CELL UNCORRECTABLE ERROR COUNTER ADDRESS 0X55
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Symbol uncorCnt[7] uncorCnt[6] uncorCnt[5] uncorCnt[4] uncorCnt[3] uncorCnt[2] uncorCnt[1] uncorCnt[0] Function
DEFAULT = 8'BXXXXXXXX
Uncorrectable HEC error count bit Uncorrectable HEC error count bit Uncorrectable HEC error count bit Uncorrectable HEC error count bit Uncorrectable HEC error count bit Uncorrectable HEC error count bit Uncorrectable HEC error count bit Uncorrectable HEC error count bit
NOTE: 1. uncorCnt[7:0] Uncorrectable HEC error count register. This is a cumulative error counter keeping track of errors from the previous poll of these registers. The error count is polled by writing to either of the HEC error registers (`h54 or `h55), or to address `h00. Such a write transfers accumulated errors to a holding register which may be read later, and the registers are cleared. This transfer and reset of the registers are done such that coincident events are not lost. All error registers in the receive sections of the transmission convergence blockor the cell delineation block may be polled by a write to the master register `h00.
RECEIVE CELL COUNTER DEFAULT = 19'H00000 ADDRESS 0X56
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Symbol cellCnt[7] cellCnt[6] cellCnt[5] cellCnt[4] cellCnt[3] cellCnt[2] cellCnt[1] cellCnt[0] Function Receive cell counter bit Receive cell counter bit Receive cell counter bit Receive cell counter bit Receive cell counter bit Receive cell counter bit Receive cell counter bit Receive cell counter bit
ADDRESS 0X57
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Symbol cellCnt[15] cellCnt[14] cellCnt[13] cellCnt[12] cellCnt[11] cellCnt[10] cellCnt[9] cellCnt[8] Function Receive cell counter bit Receive cell counter bit Receive cell counter bit Receive cell counter bit Receive cell counter bit Receive cell counter bit Receive cell counter bit Receive cell counter bit
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IDT77155 155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
ADVANCED INFORMATION Commercial Temperature Range
ADDRESS 0X58
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type -- -- -- -- -- R R R Symbol -- -- -- -- -- cellCnt[18] cellCnt[17] cellCnt[16] Function Reserved Reserved Reserved Reserved Reserved Receive cell counter bit Receive cell counter bit Receive cell counter bit
NOTE: 1.cellCnt [18:0] Receive cell counter of the number of cells passed thru' to the ATM. Cells filtered due to HEC errors or idle/unassigned cells are not counted. This is a cumulative counter keeping track of rx cells from the previous poll of these registers. The count is polled by writing to either of these registers (`h56, `h57, or `h58), the HEC error registers, or to address `h00. Such a write transfers accumulated errors to a holding register which may be read later, and the registers are cleared. This transfer and reset of the registers are done such that coincident events are not lost. All error/count registers in the receive sections of the transmission convergence block or the cell delineation block may be polled by a write to the master register `h00.
RECEIVE CELL CONFIGURATION REGISTER ADDRESS 0X59
Bit Bit 7 Type R/W Symbol GFCen[3]
DEFAULT = 8'B11111100
Function GFC enable bits. This determines which GFC bits are presented on the RGFC output. If a GFCen bit is a logic one, the RGFC output presents appropriate bit location the state of the associated GFC bit in the current cell.
Bit 6 Bit 5 Bit 4 Bit 3
R/W R/W R/W R/W
GFCen[2] GFCen[1] GFCen[0] FixSen Fixed stuff column control for STS-1 mode. When asserted high, the column 30 and 59 of the received SPE are assigned as fixed stuff columns. If FixSen is low, Column 30 and 59 are assigned as ATM payload columns. RCA level control. When asserted to a logic one, a high to low transition on RCA indicates the receive FIFO is empty. When a logic zero, a high to low transition on RCA indicates the receive FIFO in almost empty and contains only 4 more bytes to be read. HEC filter bits. It indicates the number of consecutive error free cells required in the detection mode before reverting back to the correction mode, of the HEC verification state machine. HECfltr[1:0] 00 01 10 11 Cell acceptance threshold one ATM cell with correct HEC to revert to the connection mode. This cell is accepted. two ATM cells with correct HEC to revert to the correction mode. The last cell is accepted four ATM cells with correct HEC to revert to the correction mode. The last cell is accepted eight ATM cells with correct HEC to revert to the correction mode. The last cell is accepted
Bit 2
R/W
RCA level
Bit 1
R/W
HECftr[1]
Bit 0
R/W
HECftr[0]
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RECEIVE ID ADDRESS REGISTER ADDRESS 0X5A
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Type -- -- -- -- -- -- R/W Symbol -- -- -- -- -- -- IDAddr[1]
DEFAULT = 8'B00000000
Function Reserved Reserved Reserved Reserved Reserved Reserved Device ID value for the receive portion of the receive UTOPIA logic. In multi-PY mode, the appropriate receive UTOPIA signals are driven as per UTOPIA level 2 protocol when the RXADDR bus value matches the value in this register. This has no effect in single-PHY mode.
Bit 0
R/W
IDAddr[0]
TRANSMIT CELL CONTROL REGISTER ADDRESS 0X60
Bit Bit 7 Type R/W Symbol fovrIEn
DEFAULT = 8'B00000100
Function Transmit FIFO overrun interrupt enable. Enables the generation of an interrupt due to a FIFO overrun or when the TSOC input is sampled high during any position other than the first byte. Start of cell interrupt. This bit is set high when the TSOC input is sampled high during any position other than the first byte. When such a condition occurs, the cell delineation logic assumes the new SOC signal is the start of a new cell, and the previous few bytes are discarded. Thus, cell delineation is performed in the transmit direction also. This bit is cleared after a read of this register. Transmit FIFO overrun interrupt. This bit is cleared after a read to this register. Invert the HEC bytes before transmission for diagnostic purposes when this bit is set to a logic one. Disables the generation & insertion of the of the header error check sequence. Controls the addition of the coset polynomial. When a logic one, the coset polynomial is added to the header prior to transmission. Controls the descrambling of the cell payload. When asserted high, payload scrambling is disabled. Reset tx FIFO. Used to reset the four cell transmit FIFO when asserted to a logic one. The FIFO ignores all writes until this bit is cleared.
Bit 6
R
socInt
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R/W R/W R/W R/W R/W
fovrInt HECInv HECdis csetAdd scrDis txFIFOrst
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IDT77155 155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
ADVANCED INFORMATION Commercial Temperature Range
TRANSMIT CELL IDLE/UNASSIGNED CELL HEADER PATTERN ADDRESS 0X61
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Symbol GFCtx[3] GFCtx[2] GFCtx[1] GFCtx[0] PTItx[2] PTItx[1] PTItx[0] CLPtx
DEFAULT = 8'B00000000
Function GFC Bit 3 to be inserted in GFC of transmit header for idle cell GFC Bit 2 to be inserted in GFC of transmit header for idle cell GFC Bit 1 to be inserted in GFC of transmit header for idle cell GFC Bit 0 to be inserted in GFC of transmit header for idle cell PTI Bit 2 to be inserted in PTI of transmit header for idle cell PTI Bit 1 to be inserted in PTI of transmit header for idle cell PTI Bit 0 to be inserted in PTI of transmit header for idle cell CLP value to be inserted in CLP of transmit header for idle cell
TRANSMIT CELL IDLE/UNASSIGNED CELL PAYLOAD PATTERN ADDRESS 0X62
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Symbol idlePaylaod[7] idlePaylaod[6] idlePaylaod[5] idlePaylaod[4] idlePaylaod[3] idlePaylaod[2] idlePaylaod[1] idlePaylaod[0] Function
DEFAULT = 8'B01101010
Payload value bit 7 for transmit idle/unassigned cells Payload value bit 6 for transmit idle/unassigned cells Payload value bit 5 for transmit idle/unassigned cells Payload value bit 4 for transmit idle/unassigned cells Payload value bit 3 for transmit idle/unassigned cells Payload value bit 2 for transmit idle/unassigned cells Payload value bit 1 for transmit idle/unassigned cells Payload value bit 0 for transmit idle/unassigned cells
NOTE 1. idlePyload[7:0] payload octet of idle/unassigned cells. Idle/unassigned cells are transmitted when data cells are available to b transmitted in the tx FIFO.
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IIDT77155 155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
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TRANSMIT CELL CONFIGURATION REGISTER ADDRESS 0X63
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Type R/W R/W -- R/W R/W Symbol parity parIEn -- parInt FIFOdpth[1]
DEFAULT = 8'B000X0000
Function
Select odd or even parity for TXPRTY input. When set to logic one, it is even parity over the inputs TDAT[7:0], else it is odd parity. Transmit parity interrupt enable. When asserted, an interrupt is indicated on the INTB output if a parity error is detected. Reserved tx parity interrupt. Set when a parity interrupt is detected. This bit is cleared when this register is read. txFIFO depth control. When FIFO is filled to the specified depth, TCA is disabled. TCA is asserted only when a complete cell has been read for transmission. It is not recommended to set the FIFO depth to one cell. For minimum latency and maximum throughput, set the FIFO depth to 2 cells. FIFOdpth[1:0] 00 01 10 11 FIFO depth 4 cells 3 cells 2 cells 1 cell
Bit 2 Bit 1
R/W R/W
FIFOdpth[0] TCA level TCA level control. When asserted to a logic one, a high to low transition on TCA indicates the transmit FIFO is full. When a logic zero, a high to low transition on TCA indicates the transmit FIFO in almost full and can accept only 4 more bytes. Reserved
Bit 0
--
--
TRANSMIT CELL COUNTER DEFAULT = 19'H00000 ADDRESS 0X64
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Symbol txcellCnt[7] txcellCnt[6] txcellCnt[5] txcellCnt[4] txcellCnt[3] txcellCnt[2] txcellCnt[1] txcellCnt[0] Function Transmit cell counter bit Transmit cell counter bit Transmit cell counter bit Transmit cell counter bit Transmit cell counter bit Transmit cell counter bit Transmit cell counter bit Transmit cell counter bit
ADDRESS 0X65
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Symbol txcellCnt[15] txcellCnt[14] txcellCnt[13] txcellCnt[12] txcellCnt[11] txcellCnt[10] txcellCnt[9] txcellCnt[8] Function Transmit cell counter bit Transmit cell counter bit Transmit cell counter bit Transmit cell counter bit Transmit cell counter bit Transmit cell counter bit Transmit cell counter bit Transmit cell counter bit
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IDT77155 155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
ADVANCED INFORMATION Commercial Temperature Range
ADDRESS 0X66
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type -- -- -- -- -- R R R Symbol -- -- -- -- -- txcellCnt[18] txcellCnt[17] txcellCnt[16] Function Reserved Reserved Reserved Reserved Reserved Transmit cell counter bit Transmit cell counter bit Transmit cell counter bit
NOTE: 1. txcellCnt Transmit cell counter of the number of cells read from the transmit FIFO and inserted into the SPE. Idle/unassigned cells are not counted. This is a cumulative counter keepingtrack of tx cells from the previous poll of these registers. The count is polled by writing to either of these registers (`h64, `h65, or `h66), or to address `h00. Such a write transfers accumulated errors to a holding register which may be read later, and the registers are cleared. This transfer and reset of the registers are done such that coincident events are not lost. All error/count registers in the transmit sections of the transmission convergence block or the cell delineation block may be polled by a write tothe master register `h00.
TRANSMIT CELL CONFIGURATION REGISTER ADDRESS 0X67
Bit Bit 7 Type R/W Symbol txGFCen[3]
DEFAULT = 8'B00001000
Function
GFC enable bits. This determines which GFC bits on the TGFC input are accepted to be inserted into the transmit stream. If a GFCen bit is a logic one, the corresponding GFC input is inserted into the appropriate bit position.
Bit 6 Bit 5 Bit 4 Bit 3
R/W R/W R/W R/W
txGFCen[2] txGFCen[1] txGFCen[0] txFixSen Fixed stuff column control enable in STS-1. When asserted high, the columns 30 and 59 of the transmitted SPE contains stuff bytes. The value of the stuff byte is a fixed pattern selected by the fixByte control. Disable the insertion of the calculated H4 byte. A value of 0 is inserted for the H4 byte in the SPE. byte pattern to be inserted into the fixed stuff columns of STS-1 SPE. fixByte[1:0] 00 01 10 11 stuff bype pattern `h00 `h55 `hAA `hFF
Bit 2 Bit 1
R/W R/W
H4InsDis fixByte[1]
Bit 0
R/W
fixByte[0]
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IIDT77155 155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
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TRANSMIT ID ADDRESS REGISTER ADDRESS 0X68
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Type -- -- -- -- -- -- R/W Symbol -- -- -- -- -- -- txIDAddr[1]
DEFAULT = 8'B00000000
Function Reserved Reserved Reserved Reserved Reserved Reserved Device ID value for the transmit portion of the transmit UTOPIA logic. In multi-PHY mode, the appropriate transmit UTOPIA signals are driven as per UTOPIA level 2 protocol when the TXADDR bus value matches the value in this register. This has no effect in single-PHY mode.
Bit 0
R/W
txIDAddr[0]
RECEIVE BER STATUS/CONTROL REGISTER ADDRESS 0X70
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Type -- -- -- -- R/W R/W R/W Symbol -- -- -- -- FailIEn WarnIEn BERfail Reserved Reserved Reserved Reserved
DEFAULT = 8'B00000011
Function
Interrupt enable for BER failure. Enables the generation of an interrupt upon the detection of a BER failure condition. Interrupt enable for BER warning. Enables the generation of an interrupt upon the detection of a BER warning condition. BER failure status indication. It is initially asserted at reset. Clearing this bit triggers the BER failure algorithm. This bit is cleared when the register is read. It is also as the indication of B2 EBER. BER warning status indication. It is initially asserted at reset. Clearing this bit triggers the BER warning algorithm. This bit is cleared when the register is read.
Bit 0
R/W
BERwarn
RECEIVE BER FAIL THRESHOLD REGISTER ADDRESS 0X71
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Symbol ThldFail[7] ThldFail[6] ThldFail[5] ThldFail[4] ThldFail[3] ThldFail[2] ThldFail[1] ThldFail[0]
DEFAULT = 8'B00000000
Function Value for the failure threshold of the BER fail algorithm.
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IDT77155 155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
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RECEIVE BER FAIL WINDOW REGISTER ADDRESS 0X72
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Symbol WinFail[7] WinFail[6] WinFail[5] WinFail[4] WinFail[3] WinFail[2] WinFail[1] WinFail[0]
DEFAULT = 8'B00000000
Function Value for the window length of the BER fail algorithm.
RECEIVE BER FAIL DENOMINATOR REGISTER ADDRESS 0X73
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Symbol DenFail[7] DenFail[6] DenFail[5] DenFail[4] DenFail[3] DenFail[2] DenFail[1] DenFail[0]
DEFAULT = 16'H0000
Function
LSB value for the deniminator count for the BER fail algorithm.
ADDRESS 0X74
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Symbol DenFail[15] DenFail[14] DenFail[13] DenFail[12] DenFail[11] DenFail[10] DenFail[9] DenFail[8] Function MSB value for the deniminator count for the BER fail algorithm.
RECEIVE BER WARNING THRESHOLD REGISTER ADDRESS 0X75
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Symbol ThldWarn[7] ThldWarn[6] ThldWarn[5] ThldWarn[4] ThldWarn[3] ThldWarn[2] ThldWarn[1] ThldWarn[0]
DEFAULT = 8'B00000000
Function
Value for the failure threshold of the BER warning algorithm.
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RECEIVE BER WARNING WINDOW REGISTER ADDRESS 0X76
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Symbol WinWarn[7] WinWarn[6] WinWarn[5] WinWarn[4] WinWarn[3] WinWarn[2] WinWarn[1] WinWarn[0]
DEFAULT = 8'B00000000
Function
Value for the window length of the BER warning algorithm.
RECEIVE BER WARNING DENOMINATOR REGISTER ADDRESS 0X77
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Symbol DenWarn[7] DenWarn[6] DenWarn[5] DenWarn[4] DenWarn[3] DenWarn[2] DenWarn[1] DenWarn[0]
DEFAULT = 16'H0000
Function
LSB value for the deniminator count for the BER warning algorithm.
ADDRESS 0X78
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Symbol DenWarn[15] DenWarn[14] DenWarn[13] DenWarn[12] DenWarn[11] DenWarn[10] DenWarn[9] DenWarn[8] Function MSB value for the deniminator count for the BER warning algorithm.
OUTPUT PECL CONTROL REGISTER ADDRESS 0X7F
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type -- -- -- -- -- R/W R/W R/W Symbol -- -- -- -- -- pcctl_tc pcctl_td pcctl_r
DEFAULT = 8'B00000000
Function Reserved Reserved Reserved Reserved Reserved PECL output control for TXC+/- output. If set to logic one, the output is true PECL. the default is a rail-to-rail swing. PECL output control for TXD+/- output. If set to logic one, the output is true PECL. the default is a rail-to-rail swing. PECL output control for RXDO+/- output. If set to logic one, the output is true PECL. the default is a rail-to-rail swing.
8.03
43
IDT77155 155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
ADVANCED INFORMATION Commercial Temperature Range
SYMBOL
TFCLK frequency TFCLK duty cycle RFCLK frequency RFCLK duty cycle
DISCRIPTION
MIN.
40% 40% 40% 40% 2 10 20 5 25 5 25 150 20 1 5 1 1 1 5 5 20 5 5 1 1 1 2 -2 2 8 8 10 40
MAX. UNITS
40 60% 40 60% 60% 60% 15 MHz % MHz % % % ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 20 20 80 15 2 ns ns ns ns ns ns ns ns ns ns ns
Receive line clock duty cycle Receive line clock duty cycle tRSO tALHD tALSU tARHD tARSU tAWHD tAWSU tBB tDT tDWHD tDWSU tGHD tTHD tRHD tLRHD tLRSU tLW tLWHD tLWSU tTOV tROV tRD tRDHD tGSO tSOV tRDSU tTSU tRSU tGSU tWW Receive clock RCLK to RCP/RGFC valid Address to latch enable hold time Address to latch enable setup time Address to read hold time Address to read setup time Address to write hold time Address to write setup time Time between consecutive operations Read to output data tristate Data to write hold time Data to write setup time TGFC hold to TCLK Input hold to TFCLK applies to TSOC, TWRENB, TDAT, and TXPRTY Input hold to RFCLK applies to RRDENB Latch enable to read hold time Latch enable to read setup time Latch enable pulse width Latch enable to write hold time Latch enable to write setup time TFCLK to output valid applies to TCA RFCLK to output valid applies to RSOC, RDAT, RCA, and RXPRTY Valid read to data propagation delay Receive data hold time (RBYP high) Transmit clock TCLK to RCP valid Transmit line clock output low to transmit differential data output Receive data setup time (RBYP high) Input setup to TFCLK applies to TSOC, TWRENB, TDAT, and TXPRTY Input setup to RFCLK applies to RRDENB TGFC set up to TCLK Write pulse width
8.03
44
IIDT77155 155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
ADVANCED INFORMATION Commercial Temperature Range
tTOV
tTSU tTHD
TFCLK
TSOC
TCA
TCALEVEL0 = 1
TDAT[0:7]
X
H1
H2
P44
P45
P46
P47
P48
X
H1
TXPRTY
X
X
3497 drw 14
Figure 11. Transmit Timing for UTOPIA Interface
SYMBOL
TFCLK frequency TFCLK duty cycle tTHD tTOV tTSU
DISCRIPTION
MIN.
40% 1 1 8
MAX. UNITS
40 60% 20 MHz % ns ns ns
Input hold to TFCLK applies to TSOC, TWRENB, TDAT, and TXPRTY TFCLK to output valid applies to TCA Input setup to TFCLK applies to TSOC, TWRENB, TDAT, and TXPRTY
tRSU tROV
RFCLK tROV RSOC Z
RCA
RCALEVEL0 = 0
tRHD tROV RDAT[0:7] H1 H2 H3 P44 P45 P46 P47 P48 X H1
RXPRTY
X
3497 drw 15
Figure 12. Receive Timing for UTOPIA Interface
SYMBOL
RFCLK frequency RFCLK duty cycle tRHD tROV tRSU
DISCRIPTION
MIN.
40% 1 1 8
MAX. UNITS
40 60% 20 MHz % ns ns ns
Input hold to RFCLK applies to RRDENB RFCLK to output valid applies to RSOC, RDAT, RCA, and RXPRTY Input setup to RFCLK applies to RRDENB
8.03
45
IDT77155 155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
ADVANCED INFORMATION Commercial Temperature Range
tGSO
tGSU tGHD
TCLK
TCP
TGFC
X
GFC[3]
GFC[2]
GFC[1]
GFC[0]
X
3497 drw 16
Figure 13. Transmit GFC Serial Link Timing
SYMBOL
tGHD tGSO tGSU TGFC hold to TCLK
DISCRIPTION
Transmit clock TCLK to TCP valid TGFC set up to TCLK
MIN.
1 2 10
MAX. UNITS
ns 15 ns ns
tRSO
RCLK
RCP
RGFC
X
GFC[3]
GFC[2]
GFC[1]
GFC[0]
X
3497 drw 17
Figure 14. Receive GFC Serial Link Timing
SYMBOL
tRSO
DISCRIPTION
Receive clock RCLK to RCP/RGFC valid
MIN.
2
MAX. UNITS
15 ns
8.03
46
IIDT77155 155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
ADVANCED INFORMATION Commercial Temperature Range
tSOV TXC+ TXC-
TXD+ TXD3497 drw 18
Figure 15. Line Interface Transmit Timing
SYMBOL
DISCRIPTION
Receive line clock duty cycle (155.52 MHz or 51.84 MHz - RBYP high) ( 19.44 MHz or 6.48 MHz - RBYP low )
MIN.
40%
MAX. UNITS
60% %
tSOV
Transmit line clock output low to transmit differential data output
-2
2
ns
tRDSU RRCLK+ RRCLK-
tRDHD
RXD+ RXD3497 drw 19
Figure 16. Line Interface Receive Timing
SYMBOL
DISCRIPTION
Receive line clock duty cycle (155.52 MHz or 51.84 MHz - RBYP high) ( 19.44 MHz or 6.48 MHz - RBYP low )
MIN.
40%
MAX. UNITS
60% %
tRDHD tRDSU
Receive data hold time
(RBYP high)
1 2
ns ns
Receive data setup time (RBYP high)
8.03
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IDT77155 155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
ADVANCED INFORMATION Commercial Temperature Range
tALSU tLW A[7:0] X
tALHD
Valid Address
X
ALE tLRSU CS / RD tARSU tRD D[7:0] tDT Valid Data
3497 drw 20
tARHD tLRHD
Figure 17. Microporcessor Read Timing
SYMBOL
tALHD tALSU tARHD tARSU tDT tLRHD tLRSU tLW tRD
DISCRIPTION
Address to latch enable hold time Address to latch enable setup time Address to read hold time Address to read setup time Read to output data tristate Latch enable to read hold time Latch enable to read setup time Latch enable pulse width Valid read to data propagation delay
MIN.
10 20 5 25 20 5 5 20
MAX. UNITS
ns ns ns ns ns ns ns ns 80 ns
SYMBOL
tBB
DISCRIPTION
Time between consecutive operations
MIN.
150
MAX. UNITS
ns
8.03
48
IIDT77155 155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
ADVANCED INFORMATION Commercial Temperature Range
tALSU tLW A[7:0] X
tALHD
Valid Address
X
ALE tLWSU / tAWSU tDWSU D[7:0] X tDWHD Valid Data X
3497 drw 21
tWW
tAWHD tLWHD
Figure 18. Microprocessor Write Timing
SYMBOL
tALHD tALSU tAWHD tAWSU tDWHD tDWSU tLW tLWHD tLWSU tWW
DISCRIPTION
Address to latch enable hold time Address to latch enable setup time Address to write hold time Address to write setup time Data to write hold time Data to write setup time Latch enable pulse width Latch enable to write hold time Latch enable to write setup time Write pulse width
MIN.
10 20 5 25 1 5 20 5 5 40
MAX. UNITS
ns ns ns ns ns ns ns ns ns ns
SYMBOL
tBB
DISCRIPTION
Time between consecutive operations
MIN.
150
MAX. UNITS
ns
8.03
49
IDT77155 155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
ADVANCED INFORMATION Commercial Temperature Range
ORDERING INFORMATION
IDT XXXXX Device Type A Power NNN Speed A Package A Process/ Temp. Range Blank Commercial
PX
128-pin Plastic Quad Flatpack
155
Speed in Mb/s
L
Low Power CMOS
77155
155Mb/s ATM PHY SONET/SDH Framer with Clock Recovery User Network Interface 3497 drw 22
ADVANCE INFORMATION DATASHEET: DEFINITION
"Advance Information" datasheets contain initial descriptions, subject to change, for products that are in development, including features and block diagrams. Datasheet Document History 1/10/96: Initial Public Release 2/16/96: Corrected Package Designator to PQF 4/9/96: Revised Public Release 9/16/96: Corrected block diagrams, made minor text clearifications. 11/26/95: Added timing diagrams and corrected signals that are active low.
Integrated Device Technology, Inc. reserves the right to make changes to the specifications in this data sheet in order to improve design or performance and to supply the best possible product.
Integrated Device Technology, Inc.
2975 Stender Way, Santa Clara, CA 95054-3090
8.03
Telephone: (408) 727-6116
FAX 408-492-8674
50

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